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AS3956 датащи(PDF) 59 Page - ams AG

номер детали AS3956
подробное описание детали  NFC Forum Compliant Dynamic Tag
PDF  107 Pages
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производитель  AMSCO [ams AG]
домашняя страница  http://www.ams.com
Logo AMSCO - ams AG

AS3956 датащи(HTML) 59 Page - ams AG

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ams Datasheet
Page 59
[v1-11] 2018-Nov-14
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AS3956 − Detailed Description
SPI Interface
Communication between AS3956 and microcontroller can be
done via a four-wire Serial Peripheral Interface (SPI) and an
additional interrupt signal. AS3956 acts an SPI slave device, and
it can request MCU attention by sending an interrupt (pin IRQ).
Please note a 100k ohm pull down resistor is recommended to
be connected to the IRQ pin to prevent IRQ from floating when
/SS is high.The SCLK frequency can be between 100 kHz and 5
MHz.
In addition to Schmitt triggers on all digital input lines a glitch
suppression filter is implemented on the SCLK input and
suppresses glitches of length Tgs.
Figure 55:
SPI and Interrupt Signals
SPI interface is in reset mode when signal /SS is high, and it is
enabled when /SS is low. It is recommended to keep signal /SS
high whenever the SPI interface is not used. MOSI is sampled
at the falling edge of SCLK. All communication is done in 8-bit
blocks (bytes). First three bits of first byte transmitted after /SS
high to low transition define SPI operation mode. MSB bit is
always transmitted first (valid for address and data). Read and
Write modes support address auto incrementing, which means
that in case some additional data bytes may be sent (read), they
are written to (read from) addresses incremented by 1 after the
address and first data byte.
SPI interface supports the following modes:
• Internal registers read and write
• EEPROM read and write
• Buffer read and write
• Direct commands
Note that in case when logic and EEPROM are supplied from the
VP_IO, the only SPI operations permitted are reading and
writing of EEPROM and registers (see also Power Management).
Name
Signal
Signal Level
Description
/SS
Digital Input with pull-up
CMOS
SPI enable (active low)
MOSI
Digital Input
CMOS
Serial data input
MISO
Digital Output with tristate
CMOS
Serial data output
SCLK
Digital Input
CMOS
Clock for serial communication
IRQ
Digital Output
CMOS
Interrupt output pin (active high)



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