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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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MPC8544EBVTALFA датащи(PDF) 29 Page - NXP Semiconductors |
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MPC8544EBVTALFA датащи(HTML) 29 Page - NXP Semiconductors |
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29 / 117 page  MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 8 Freescale Semiconductor 29 Enhanced Three-Speed Ethernet (eTSEC), MII Management 8.4.2 SGMII Receive AC Timing Specifications Table 27 provides the SGMII receive AC timing specifications. Source synchronous clocking is not supported. Clock is recovered from the data. Figure 9 shows the SGMII receiver input compliance mask eye diagram. Figure 9. Receive Input Compliance Mask Table 27. SGMII Receiver AC Timing Specifications At recommended operating conditions with XVDD_SRDS2 = 1.0 V ± 5%. Parameter Symbol Min Typ Max Unit Notes Deterministic jitter tolerance JD 0.37 — — UI p-p 1 Combined deterministic and random jitter tolerance JDR 0.55 — — UI p-p 1 Sinusoidal jitter tolerance Jsin 0.1 — — UI p-p 1 Total jitter tolerance JT 0.65 — — UI p-p 1 Bit error ratio BER — — 10-12 —— Unit interval UI 799.92 800 800.08 ps 2 AC coupling capacitor CTX 5— 200 nF 3 Notes: 1. Measured at receiver. 2. Each UI value is 800 ps ± 100 ppm. 3. The external AC coupling capacitor is required. It’s recommended to be placed near the device transmitter outputs. 01 0.275 0.4 0.6 0.725 0 Vrx_diffpp_max/2 Vrx_diffpp_min/2 –Vrx_diffpp_min/2 –Vrx_diffpp_max/2 Time (UI) |
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