 |
поискавой системы для электроныых деталей |
|
|
поискавой системы для электроныых деталей |
|
CDCDB803 датащи(PDF) 3 Page - Texas Instruments |
|
|
|
|||||||||||||||||||||||||||||
CDCDB803 датащи(HTML) 3 Page - Texas Instruments |
|
|
3 / 31 page  5 Pin Configuration and Functions CDCDB803 TOP VIEW 48-pin QFN Package DAP = GND OE#0 CK6_N CK6_P VDD CK5_N CK5_P OE5# OE4# CK4_N CK4_P VDD CK3_N CK3_P CKPWRGD_PD# VDDR CLKIN_P CLKIN_N SADR0 SMBCLK SADR1 SMBDAT NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 36 35 34 33 32 31 30 29 28 27 26 25 48 47 46 45 44 43 42 41 40 39 38 37 NC VDD Figure 5-1. CDCDB803 RSL Package 48-Pin VQFN Top View Table 5-1. Pin Functions PIN I/O TYPE(2) DESCRIPTION NAME NO. INPUT CLOCK CLKIN_P 3 I LP-HCSL differential clock input. Typically connected directly to the differential output of clock source. CLKIN_N 4 I OUTPUT CLOCKS CK0_P 13 O LP-HCSL differential clock output of channel 0. Typically connected directly to PCIe differential clock input. If unused, the pins can be left no connect. CK0_N 14 O CK1_P 16 O LP-HCSL differential clock output of channel 1. Typically connected directly to PCIe differential clock input. If unused, the pins can be left no connect. CK1_N 17 O CK2_P 21 O LP-HCSL differential clock output of channel 2. Typically connected directly to PCIe differential clock input. If unused, the pins can be left no connect. CK2_N 22 O CK3_P 25 O LP-HCSL differential clock output of channel 3. Typically connected directly to PCIe differential clock input. If unused, the pins can be left no connect. CK3_N 26 O CK4_P 28 O LP-HCSL differential clock output of channel 4. Typically connected directly to PCIe differential clock input. If unused, the pins can be left no connect. CK4_N 29 O CK5_P 32 O LP-HCSL differential clock output of channel 5. Typically connected directly to PCIe differential clock input. If unused, the pins can be left no connect. CK5_N 33 O CK6_P 35 O LP-HCSL differential clock output of channel 6. Typically connected directly to PCIe differential clock input. If unused, the pins can be left no connect. CK6_N 36 O CK7_P 39 O LP-HCSL differential clock output of channel 7. Typically connected directly to PCIe differential clock input. If unused, the pins can be left no connect. CK7_N 40 O www.ti.com CDCDB803 SNAS820 – AUGUST 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: CDCDB803 |
|
ссылки URL |
| Вашему бизинису помогли Аллдатащит? [ DONATE ] |
Что такое Аллдатащит | реклама | контакт | Конфиденциальность | Ссылка на техническое описание | обмен ссыками | поиск по производителю All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Russian ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
