The SMBus address pins are sampled when PWRGD is set to 1. See Table 8-1 for address pin configuration.

The address can only be changed by power cycling the device.

Table 8-1. SMBus Address Assignment

SADR1

SADR0

SMBus ADDRESS : WRITE

OPERATION (READ/WRITE=0)

SMBus ADDRESS : READ

OPERATION (READ/WRITE=1)

L

L

0xD8

0xD9

L

M

0xDA

0xDB

L

H

0xDE

0xDF

M

L

0xC2

0xC3

M

M

0xC4

0xC5

M

H

0xC6

0xC7

H

L

0xCA

0xCB

H

M

0xCC

0xCD

H

H

0xCE

0xCF

8.4 Device Functional Modes

8.4.1 CKPWRGD_PD# Function

The CKPWRGD_PD# pin is used to set two state variables inside of the device: PWRGD and PD#. The PWRGD

and PD# variables control which functions of the device are active at any time, as well as the state of the input

and output pins.

The PWRGD and PD# states are multiplexed on the CKPWRGD_PD# pin. CKPWRGD_PD# must remain below

conditions. After CKPWRGD_PD# is set high, a valid CLKIN must be present to use PD#.

The first rising edge of the CKPWRGD_PD# pin sets PWRGD = 1. After PWRGD is set to 1, the

CKPWRGD_PD# pin is used to assert PD# mode only. PWRGD variable will only be cleared to 0 with the

PWRGD

PD#

CKPWRGD_PD#

VDD/VDDR

Figure 8-1. PWRGD and PD# State Changes

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CDCDB803

SNAS820 – AUGUST 2021

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