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Table 2. Periodic Interrupt Rate and Square-Wave Output Frequency

EXT. REG. B

SELECT BITS REGISTER A

E32K

RS3

RS2

RS1

RS0

INTERRUPT RATE

SQW OUTPUT

FREQUENCY

0

0

0

0

0

None

None

0

0

0

0

1

3.90625ms

256Hz

0

0

0

1

0

7.8125ms

128Hz

0

0

0

1

1

122.070

µs

8.192kHz

0

0

1

0

0

244.141

µs

4.096kHz

0

0

1

0

1

488.281

µs

2.048kHz

0

0

1

1

0

976.5625

µs

1.024kHz

0

0

1

1

1

1.953125ms

512Hz

0

1

0

0

0

3.90625ms

256Hz

0

1

0

0

1

7.8125ms

128Hz

0

1

0

1

0

15.625ms

64Hz

0

1

0

1

1

31.25ms

32Hz

0

1

1

0

0

62.5ms

16Hz

0

1

1

0

1

125ms

8Hz

0

1

1

1

0

250ms

4Hz

0

1

1

1

1

500ms

2Hz

1

X

X

X

X

(See Note)

32.768kHz

Note: RS3–RS0 determine periodic interrupt rates as listed for E32K = 0.

The third method uses a periodic interrupt to determine if an update cycle is in progress. The UIP bit in

Register A is set high between the setting of the PF bit in Register C (see Figure 3). Periodic interrupts

data is not read during the update cycle.

Figure 3. Update-Ended and Periodic Interrupt Relationship