SH7041A datasheet(261/923 Pages) RENESAS

номер детали	SH7041A

подробное описание детали	Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

PDF	923 Pages

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производитель	RENESAS [Renesas Technology Corp]

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• Bits 15 and 14—Destination Address Mode 1, 0 (DM1 and DM0): These bits specify

increment/decrement of the DMA transfer destination address. These bit specifications are

ignored when transferring data from an external device to address space in single address

mode.

Bit 15: DM1

Bit 14: DM0

Description

Destination address fixed (initial value)

Destination address incremented (+1 during 8-bit transfer, +2

during 16-bit transfer, +4 during 32-bit transfer)

Destination address decremented (–1 during 8-bit transfer, –2

during 16-bit transfer, –4 during 32-bit transfer)

Setting prohibited

• Bits 13 and 12—Source Address Mode 1, 0 (SM1 and SM0): These bits specify

increment/decrement of the DMA transfer source address. These bit specifications are ignored

when transferring data from an external device to address space in single address mode.

Bit 13: SM1

Bit 12: SM0

Description

Source address fixed (initial value)

Source address incremented (+1 during 8-bit transfer, +2

during 16-bit transfer, +4 during 32-bit transfer)

Source address decremented (–1 during 8-bit transfer, –2

during 16-bit transfer, –4 during 32-bit transfer)

Setting prohibited

When the transfer source is specified at an indirect address, specify in source address register 3

(SAR3) the actual storage address of the data you want to transfer as the data storage address

(indirect address).

During indirect address mode, SAR3 obeys the SM1/SM0 setting for increment/decrement. In this

case, SAR3’s increment/decrement is fixed at +4/–4 or 0, irrespective of the transfer data size

specified by TS1 and TS0.

SH7041A датащи(PDF) 261 Page - Renesas Technology Corp