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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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SH7041A датащи(PDF) 235 Page - Renesas Technology Corp |
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SH7041A датащи(HTML) 235 Page - Renesas Technology Corp |
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235 / 923 page  197 10.4.5 Refresh Timing The bus state controller is equipped with a function to control refreshes of DRAM. CAS-before- RAS (CBR) refresh or self-refresh can be selected by setting the RTCSR’s RMD bit. CAS-before-RAS Refresh: For CBR refreshes, set the RCR’s RMD bit to 0 and the RFSH bit to 1. Also write the values in RTCNT and RTCOR necessary to fulfill the refresh interval prescribed for the DRAM being used. When a clock is selected with the CKS2–CKS0 bits of the RSTCR, RTCNT starts counting up from the value at that time. The RTCNT value is constantly compared to the RTCOR value and a CBR refresh is performed when the two match. RTCNT is cleared at that time and the count starts again. Figure 10.15 shows the timing for the CBR refresh operation. The number of RAS assert cycles in the refresh cycle is set by the TRAS1, TRAS0 bits of the DCR. CK CASx RAS TRp TRr1 TRr2 TRc TRc Figure 10.15 CAS-Before-RAS Refresh Timing (TRAS1, TRAS0 = 0, 0) |
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