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SH7041A датащи(PDF) 229 Page - Renesas Technology Corp

номер детали SH7041A
подробное описание детали  Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)
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производитель  RENESAS [Renesas Technology Corp]
домашняя страница  http://www.renesas.com
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SH7041A датащи(HTML) 229 Page - Renesas Technology Corp

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10.4.3
Wait State Control
Wait state insertion during DRAM space access is controlled by setting the TPC, RCD, DWW1,
DWW0, DWR1, and DWR0 bits of the DCR. TPC and RCD are common to both reads and
writes. The timing with waits inserted is shown in figures 10.8 through 10.11. External waits can
be inserted at the time of software waits 2, 3. The sampling location is the same as that of ordinary
space: at one cycle before the Tc2 cycle clock rise. Wait cycles are extended by external waits.
Tp
Tr
Tc1
Tcw1
Tc2
CK
Write
Read
Address
Data
RAS
CASx
RDWR
Data
RDWR
CASx
RAS
Row
Column
Figure 10.8 DRAM Bus Cycle (Normal Mode, TPC = 0, RCD = 0, One Wait)



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