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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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SH7041A датащи(PDF) 201 Page - Renesas Technology Corp |
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SH7041A датащи(HTML) 201 Page - Renesas Technology Corp |
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201 / 923 page  163 Section 10 Bus State Controller (BSC) 10.1 Overview The bus state controller (BSC) divides up the address spaces and outputs control for various types of memory. This enables memories like DRAM, SRAM, and ROM to be linked directly to the LSI without external circuitry. 10.1.1 Features The BSC has the following features: • Address space is divided into five spaces A maximum linear 2 Mbytes for on-chip ROM effective mode, and a maximum linear 4-Mbyte for on-chip ROM ineffective mode for address space CS0 A maximum linear 4 Mbytes for each of the address spaces CS1–CS3 A maximum linear 16 Mbytes for DRAM dedicated space Bus width can be selected for each space (8, 16, or 32 bits) Wait states can be inserted by software for each space Wait states can be inserted via the WAIT pin in external memory spce accesses. Outputs control signals for each space according to the type of memory connected • On-chip ROM and RAM interfaces On-chip RAM access of 32 bits in 1 state On-chip ROM access of 32 bits in 1 state • Direct interface to DRAM Multiplexes row/column addresses according to DRAM capacity Supports high-speed page mode and RAS down mode • Access control for each type of memory, peripheral LSI Address/data multiplex function • Refresh Supports CAS-before-RAS refresh (auto-refresh) and self-refresh • Refresh counter can be used as an interval timer Interrupt request generated upon compare match (CMI interrupt request signal) |
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