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SH7041A датащи(PDF) 127 Page - Renesas Technology Corp

номер детали SH7041A
подробное описание детали  Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)
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89
5.1.3
Exception Processing Vector Table
Before exception processing begins running, the exception processing vector table must be set in
memory. The exception processing vector table stores the start addresses of exception service
routines. (The reset exception processing table holds the initial values of PC and SP.)
All exception sources are given different vector numbers and vector table address offsets, from
which the vector table addresses are calculated. During exception processing, the start addresses of
the exception service routines are fetched from the exception processing vector table, which
indicated by this vector table address.
Table 5.3 shows the vector numbers and vector table address offsets. Table 5.4 shows how vector
table addresses are calculated.
Table 5.3
Exception Processing Vector Table
Exception Sources
Vector
Numbers
Vector Table Address Offset
Power-on reset
PC
0
H'00000000–H'00000003
SP
1
H'00000004–H'00000007
Manual reset
PC
2
H'00000008–H'0000000B
SP
3
H'0000000C–H'0000000F
General illegal instruction
4
H'00000010–H'00000013
(Reserved by system)
5
H'00000014–H'00000017
Slot illegal instruction
6
H'00000018–H'0000001B
(Reserved by system)
7
H'0000001C–H'0000001F
(Reserved by system)
8
H'00000020–H'00000023
CPU address error
9
H'00000024–H'00000027
DMAC/DTC address
error
10
H'00000028–H'0000002B
Interrupts
NMI
11
H'0000002C–H'0000002F
User break
12
H'00000030–H'00000033
(Reserved by system)
13
:
31
H'00000034–H'00000037
:
H'0000007C–H'0000007F
Trap instruction (user vector)
32
:
63
H'00000080–H'00000083
:
H'000000FC–H'000000FF



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