SH7041A datasheet(126/923 Pages) RENESAS

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5.1.2

Exception Processing Operations

The exception processing sources are detected and begin processing according to the timing

shown in table 5.2.

Table 5.2

Timing of Exception Source Detection and the Start of Exception Processing

Exception

Source

Timing of Source Detection and Start of Processing

Reset

Power-on reset

Starts when the

RES pin changes from low to high.

Manual reset

Starts when the

RES pin is high and the MRES pin changes

from low to high.

Address error

Detected when instruction is decoded and starts when the

previous executing instruction finishes executing.

Interrupts

Detected when instruction is decoded and starts when the

previous executing instruction finishes executing.

Instructions

Trap instruction

Starts from the execution of a TRAPA instruction.

General illegal

instructions

Starts from the decoding of undefined code anytime except after

a delayed branch instruction (delay slot).

Illegal slot

instructions

Starts from the decoding of undefined code placed in a delayed

branch instruction (delay slot) or of instructions that rewrite the

PC.

When exception processing starts, the CPU operates as follows:

1. Exception processing triggered by reset:

The initial values of the program counter (PC) and stack pointer (SP) are fetched from the

exception processing vector table (PC and SP are respectively the H'00000000 and

H'00000004 addresses for power-on resets and the H'00000008 and H'0000000C addresses for

manual resets). See section 5.1.3, Exception Processing Vector Table, for more information. 0

is then written to the vector base register (VBR) and 1111 is written to the interrupt mask bits

(I3–I0) of the status register (SR). The program begins running from the PC address fetched

from the exception processing vector table.

2. Exception processing triggered by address errors, interrupts and instructions:

SR and PC are saved to the stack indicated by R15. For interrupt exception processing, the

interrupt priority level is written to the SR’s interrupt mask bits (I3–I0). For address error and

instruction exception processing, the I3–I0 bits are not affected. The start address is then

fetched from the exception processing vector table and the program begins running from that

address.

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