LTC4292 datasheet(39/40 Pages) AD

номер детали	LTC4292

подробное описание детали	4-Port IEEE 802.3bt PoE PSE Controller

PDF	40 Pages

Scroll/Zoom	100%

производитель	AD [Analog Devices]

домашняя страница	http://www.analog.com

Logo

39 / 40 page

LTC4291-1/LTC4292

Rev 0

For more information www.analog.com

6.00 ±0.10

(4 SIDES)

NOTE:

1. DRAWING IS A JEDEC PACKAGE OUTLINE VARIATION OF (WJJD-2)

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE

PIN 1 TOP MARK

(SEE NOTE 6)

PIN 1 NOTCH

R = 0.45 OR

0.35

× 45°

CHAMFER

0.40 ±0.10

BOTTOM VIEW—EXPOSED PAD

4.50 REF

(4-SIDES)

4.42 ±0.10

4.42 ±0.05

0.75 ±0.05

R = 0.115

TYP

0.25 ±0.05

0.50 BSC

0.200 REF

0.00 – 0.05

(UJ40) QFN REV Ø 0406

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

0.70 ±0.05

4.50 ±0.05

(4 SIDES)

5.10 ±0.05

6.50 ±0.05

0.25 ±0.05

0.50 BSC

PACKAGE OUTLINE

R = 0.10

TYP

UJ Package

40-Lead Plastic QFN (6mm

× 6mm)

(Reference LTC DWG # 05-08-1728 Rev Ø)

PACKAGE DESCRIPTION

LTC4292 датащи(PDF) 39 Page - Analog Devices

LTC4292 датащи(HTML) 39 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

датащи скачать

ссылки URL