DS2196 datasheet(74/157 Pages) MAXIM

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DS2196

74 of 157

RMR1A/RMR2A/RMR3A: RECEIVE MARK REGISTERS FRAMER A

(Address = 2D to 2F Hex)

RMR1B/RMR2B/RMR3B: RECEIVE MARK REGISTERS FRAMER B

(Address = CD to CF Hex)

(MSB)

(LSB)

CH8

CH7

CH6

CH5

CH4

CH3

CH2

CH1

RMR1

CH16

CH15

CH14

CH13

CH12

CH11

CH10

CH9

RMR2

CH24

CH23

CH22

CH21

CH20

CH19

CH18

CH17

RMR3

SYMBOLS

POSITIONS

NAME AND DESCRIPTION

CH1-24

RMR1.0-3.7

Receive Channel Mark Control Bits

0 =do not affect the receive data associated with this channel

1 = replace the receive data associated with this channel with

either the idle code or the digital milliwatt code (depends on the

RCR2.7 bit)

12.

PROGRAMMABLE IN–BAND CODE GENERATION AND DETECTION

Each framer in the DS2196 has the ability to generate and detect a repeating bit pattern that is from one to

8 bits and 16 bits in length. To transmit a pattern, the user will load the pattern to be sent into the

Transmit Code Definition (TCD1&TCD2) registers and select the proper length of the pattern by setting

the TC0 and TC1 bits in the In–Band Code Control (IBCC) register. When generating a 1, 2, 4, 8 or

16 bit pattern both transmit code definition registers (TCD1&TCD2) must be filled with the proper code.

Generation of a 3, 5, 6 and 7 bit pattern only requires TCD1 to be filled. Once this is accomplished, the

pattern will be transmitted as long as the TLOOP control bit (CCR3.1) is enabled. Normally (unless the

transmit formatter is programmed to not insert the F–bit position) the framer will overwrite the repeating

pattern once every 193 bits to allow the F–bit position to be sent. See Figure 21-7 for more details. As

an example, if the user wished to transmit the standard “loop up” code for Channel Service Units which is

a repeating pattern of ...10000100001... then 80h would be loaded into TCD1 and the length would set to

5 bits.

Each framer can detect three separate repeating patterns. Typically, two of the detectors are used for

“loop up” and “loop down” code detection. The user will program the codes to be detected in the

Receive Up Code Definition (RUPCD1 & RUPCD2) registers and the Receive Down Code Definition

(RDNCD1 & RDNCD2) registers and the length of each pattern will be selected via the IBCC register.

There is a third detector (Spare) and it is defined and controlled via the RSCD1/RSCD2 and RSCC

registers. When detecting an 8 or 16 bit pattern both receive code definition registers must be filled with

the proper code. For 8 bit patterns both receive code definition registers will be filled with the same

value. Detection of a 1, 2, 3, 4, 5, 6 and 7 bit pattern only requires the first receive code definition

repeating pattern codes in both framed and unframed circumstances with bit error rates as high as 10E–2.

The detectors are capable of handling both F-bit inserted and F-bit overwrite patterns. Writing the least

significant byte of receive code definition register resets the integration period for that detector. The code

detector has a nominal integration period of 30 ms. Hence, after about 30 ms of receiving a valid code,

the proper status bit (LUP at SR1A/B.7 , LDN at SR1A/B.6 and LSPARE at SR1A/B.4 ) will be set to a

1. Normally codes are sent for a period of 5 seconds. It is recommend that the software poll the framer

every 50 ms to 1000 ms until 5 seconds has elapsed to insure that the code is continuously present.

IBCCA: IN–BAND CODE CONTROL REGISTER FRAMER A

(Address = 12 Hex)

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