DS2196 datasheet(69/157 Pages) MAXIM

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DS2196

69 of 157

Each Receive Signaling Register (RS1 to RS12) reports the incoming robbed bit signaling from eight

DS0 channels. In the ESF framing mode, there can be up to four signaling bits per channel (A, B, C, and

D). In the D4 framing mode, there are only two framing bits per channel (A and B). In the D4 framing

mode, the framer will replace the C and D signaling bit positions with the A and B signaling bits from the

previous multiframe. Hence, whether the framer is operated in either framing mode, the user needs only

to retrieve the signaling bits every 3 ms. The bits in the Receive Signaling Registers are updated on

multiframe boundaries so the user can utilize the Receive Multiframe Interrupt in the Receive Status

frozen and not updated during a loss of sync condition (SR1.0=1). They will contain the most recent

signaling information before the “OOF” occurred. The signaling data reported in RS1 to RS12 is also

available at the RSER pin.

TS1A TO TS12A: TRANSMIT SIGNALING REGISTERS FRAMER A

(Address = 70 to 7B Hex)

TS1B TO TS12B: TRANSMIT SIGNALING REGISTERS FRAMER B

(Address = F0 to FB Hex)

(MSB)

(LSB)

A(8)

A(7)

A(6)

A(5)

A(4)

A(3)

A(2)

A(1)

TS1

A(16)

A(15)

A(14)

A(13)

A(12)

A(11)

A(10)

A(9)

TS2

A(24)

A(23)

A(22)

A(21)

A(20)

A(19)

A(18)

A(17)

TS3

B(8)

B(7)

B(6)

B(5)

B(4)

B(3)

B(2)

B(1)

TS4

B(16)

B(15)

B(14)

B(13)

B(12)

B(11)

B(10)

B(9)

TS5

B(24)

B(23)

B(22)

B(21)

B(20)

B(19)

B(18)

B(17)

TS6

A/C(8)

A/C(7)

A/C(6)

A/C(5)

A/C(4)

A/C(3)

A/C(2)

A/C(1)

TS7

A/C(16)

A/C(15)

A/C(14)

A/C(13)

A/C(12)

A/C(11)

A/C(10)

A/C(9)

TS8

A/C(24)

A/C(23)

A/C(22)

A/C(21)

A/C(20)

A/C(19)

A/C(18)

A/C(17)

TS9

B/D(8)

B/D(7)

B/D(6)

B/D(5)

B/D(4)

B/D(3)

B/D(2)

B/D(1)

TS10

B/D(16)

B/D(15)

B/D(14)

B/D(13)

B/D(12)

B/D(11)

B/D(10)

B/D(9)

TS11

B/D(24)

B/D(23)

B/D(22)

B/D(21)

B/D(20)

B/D(19)

B/D(18)

B/D(17)

TS12

SYMBOL

POSITION

NAME AND DESCRIPTION

D(24)

TS12.7

Signaling Bit D in Channel 24

A(1)

TS1.0

Signaling Bit A in Channel 1

Each Transmit Signaling Register (TS1 to TS12) contains the Robbed Bit signaling for eight DS0

channels that will be inserted into the outgoing stream if enabled to do so via TCR1.4. In the ESF

framing mode, there can be up to four signaling bits per channel (A, B, C, and D). On multiframe

boundaries, the framer will load the values present in the Transmit Signaling Register into an outgoing

signaling shift register that is internal to the device. The user can utilize the Transmit Multiframe

Interrupt in Status Register 2 (SR2.6) to know when to update the signaling bits. In the ESF framing

mode, the interrupt will come every 3 ms and the user has a full 3ms to update the TSRs. In the D4

framing mode, there are only two framing bits per channel (A and B). However in the D4 framing mode,

the framer uses the C and D bit positions as the A and B bit positions for the next multiframe. The framer

will load the values in the TSRs into the outgoing shift register every other D4 multiframe.

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