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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ADF4212LBRU датащи(PDF) 3 Page - Analog Devices |
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ADF4212LBRU датащи(HTML) 3 Page - Analog Devices |
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3 / 20 page  REV. 0 –3– ADF4212L (VDD1 = VDD2 = 2.7 V to 3.3 V; VP1, VP2 = VDD to 5.5 V ; AGNDRF = DGNDRF = AGNDIF = DGNDIF = 0 V; TA = TMIN to TMAX, unless otherwise noted; dBm referred to 50 .) SPECIFICATIONS1 Parameter B Version B Chips2 Unit Test Conditions/Comments NOISE CHARACTERISTICS RF Phase Noise Floor 3 –170 –170 dBc/Hz typ @ 25 kHz PFD Frequency –162 –162 dBc/Hz typ @ 200 kHz PFD Frequency Phase Noise Performance 4 @ VCO Output IF: 540 MHz Output 5 –89 –89 dBc/Hz typ @ 1 kHz Offset and 200 kHz PFD Frequency IF: 900 MHz Output 6 –87 –87 dBc/Hz typ See Note 9 RF: 900 MHz Output 6 –89 –89 dBc/Hz typ See Note 9 RF: 1750 MHz Output 7 –84 –84 dBc/Hz typ See Note 9 RF: 2400 MHz Output 8 –87 –87 dBc/Hz typ @ 1 kHz Offset and 1 MHz PFD Frequency Spurious Signals IF: 540 MHz Output 5 –88/–90 –88/–90 dB typ @ 200 kHz/400 kHz and 200 kHz PFD Frequency IF: 900 MHz Output 6 –90/–94 –90/–94 dB typ See Note 9 RF: 900 MHz Output 6 –90/–94 –90/–94 dB typ See Note 9 RF: 1750 MHz Output 7 –80/–82 –80/–82 dB typ See Note 9 RF: 2400 MHz Output 8 –80/–82 –80/–82 dB typ @ 200 kHz/400 kHz and 200 kHz PFD Frequency NOTES 1Operating temperature range is as follows: B Version: –40 °C to +85°C 2The B Chip specifications are given as typical values. 3The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20logN (where N is the N divider value). See TPC 14. 4The phase noise is measured with the EVAL-ADF4210/12/13EB Evaluation Board and the HP8562E Spectrum Analyzer. The spectrum analyzer provides the REFIN for the synthesizer. (fREFOUT = 10 MHz @ 0 dBm) 5f REFIN = 10 MHz; fPFD = 200 kHz; Offset Frequency = 1 kHz; f IF = 540 MHz; N = 2700; Loop B/W = 20 kHz 6f REFIN = 10 MHz; fPFD = 200 kHz; Offset Frequency = 1 kHz; f RF = 900 MHz; N = 4500; Loop B/W = 20 kHz 7f REFIN = 10 MHz; fPFD = 200 kHz; Offset Frequency = 1 kHz; f RF = 1750 MHz; N = 8750; Loop B/W = 20 kHz 8f REFIN = 10 MHz; fPFD = 1 MHz; Offset Frequency = 1 kHz; f RF = 2400 MHz; N = 9800; Loop B/W = 20 kHz 9Same conditions as listed on the preceding line. Specifications subject to change without notice. TIMING CHARACTERISTICS Limit at TMIN to TMAX Parameter (B Version) Unit Test Conditions/Comments t1 10 ns min DATA to CLOCK Set-Up Time t2 10 ns min DATA to CLOCK Hold Time t3 25 ns min CLOCK High Duration t4 25 ns min CLOCK Low Duration t5 10 ns min CLOCK to LE Set-Up Time t6 20 ns min LE Pulsewidth Guaranteed by design but not production tested. Specifications subject to change without notice. CLOCK DATA LE LE t3 t1 t2 t4 t5 t6 DB20 (MSB) DB19 DB2 (CONTROL BIT C2) DB1 DB0 (LSB) (CONTROL BIT C1) Figure 1. Timing Diagram (VDD1 = VDD2 = 2.6 V to 3.3 V; VP1, VP2 = VDD to 5.5 V ; AGNDRF = DGNDRF = AGNDIF = DGNDIF = 0 V; TA = TMIN to TMAX, unless otherwise noted; dBm referred to 50 .) |
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