USB5926CSLASHKD datasheet(42/65 Pages) MICROCHIP

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2019 - 2021 Microchip Technology Inc.

DS00003190B-page 42

USB5926C

8.7.2.2

Link Timeout Reset

Port Splitting is intended for use with embedded USB 3.x devices only. When Port Splitting is enabled, the hub constantly

monitors the USB 3.2 Gen 1 Link to see if a valid USB 3.2 Gen 1 Link is established. If there is no valid USB 3.2 Gen 1

Link for a configured amount of time (see below), then the hub will toggle assertion of the associated “

PRTPWRx-

_USB3_SPLIT” pin in an attempt to reset the embedded USB 3.2 Gen 1 device and re-establish the USB 3.2 Gen 1 Link.

The timer is always reset and restarted whenever the timeout occurs.

A valid USB 3.2 Gen 1 link is qualified by the LTSSM_STATE register status for the port. A normal Link will actively

switch through many Link states.

If the hub detects that the Link is staying in one of the following Link states the entire duration of the timeout timer, then

the Link is stuck in an invalid state and

PRTPWRx_USB3_SPLIT will be toggled in order to attempt to re-establish the

Link.

• SIS.Disabled(0x4)

• Rx.Detect(0x5)

• SS.Inactive(0x6)

• Polling(0x7)

• Recovery(0x8)

• HotReset (0x9)

The Link Timeout Reset value is configured via register 0x4171 and can be overridden by OTP. The default value is

0x05, which selects a Timeout value of 1 second. Setting the register to 0x00 will disable the Link Timeout Reset feature.

The duration of the Link reset (time which

PRTPWRx_USB3_SPLIT signal stays low) can be configured in register

0x4176. The default duration is 400ms with a configurable range of 350ms to 2.9s.

TABLE 8-7:

GLOBAL PORT SPLIT ENABLE REGISTER

PORTSPLITENABLEFLAG

(0x4141 - RESET = 0x00)

Global Port Split Enable

BIT

Name

R/W

Description

7:1

Reserved

GLOBAL_PORT_SPLIT_EN

R/W

0 = Port Split feature global disable

1 = Port Split feature global enable

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