SC2200 datasheet(3/11 Pages) MAXIM

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RF Range for Maximum Correction—698MHz to 2700MHz

(Operation at TA = +25°C, VAVDD18 = 1.8V, VDVDDIO = 1.8V, VDVDD18 = 1.8V and 20MHz external clock, unless otherwise specified.)

Digital I/O—DC Characteristics

(Guaranteed performance across worst-case supply voltage and temperature range, unless otherwise specified.)

Note 9:

Peak power is defined as the 10-4 point on the CCDF (complementary cumulative distribution function) of the signal.

Note 10: PA operated at maximum power.

Note 11: PRFOUT_PK must be below +7dBm pk under all conditions.

Note 12: Only when the internal through path is enabled.

Note 13: IO type (input/output, pull up/down, push pull, open drain…) is programmable for DIO* pins. Refer to the Programming

Guide and HW Design Guide for more information.

Note 14: User can configure the SC2200 to accept the following external clock frequencies: 10, 13, 15.36, 19.2, 20, 26 and

30.72MHz. External clock frequency other than 20MHz requires programming through the SPI bus. Refer to the

Programming Guide and Hardware Design Guide for more information.

Note 13: IO type (input/output, pull up/down, push pull, open drain…) is programmable for DIO* pins. Refer to the Programming

Guide and HW Design Guide for more information.

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

RFIN Peak Power

(Note 9)

PRFIN_PKL

698MHz–2200MHz (Note 10)

-3

dBm

PRFIN_PKH

2200MHz–2700MHz (Note 10)

-3

PRFINRG_PKL

Operating range, 698MHz–2200MHz

-32

PRFINRG_PKH

Operating range,

2200MHz–2700MHz

-32

RFINDLY Peak Power

(Notes 9, 11)

PRFINDLY_PK

PA operated at maximum power

-11

-8

-5

dBm

PRFINDLYRG_PK Operating range

-40

-5

RFFB Peak Power

(Note 9)

PRFFB_PK

PA operated at maximum power

-8

-4

-2

dBm

PRFFBRG_PK

Operating range

-37

-2

RFOUT Peak Power

(Note 9)

PRFOUT _PKL

PA operated at maximum power (Note 12)

698MHz–2200MHz (Note 10)

-1

dBm

PRFOUT _PKH

PA operated at maximum power (Note 12)

2200MHz–2700MHz (Note 10)

-1

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

CMOS Input Logic-Low

VIL

-0.2

0.2 x VDD

CMOS Input Logic-High

VIH

VDD = DVDDIO

VDD x 0.8

VDD x 1.1

CMOS Output Logic-High

VOH

VDD = DVDDIO

VDD x 0.9

VDD

CMOS Output Logic-Low

VOL

0.0

0.1 x VDD

CMOS Output Current

(Note 13)

IOL18/IOH18

VDVDDIO = 1.8V

-4.0

+4.0

SC2200

Dual RF Power Amplifier Linearizer (RFPAL)

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