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DA9131

High-Performance, Dual-Channel DC-DC Converter for

Mobile and Portable Applications

Datasheet

Revision 2.0

11-Aug-2021

CFR0011-120-00

29 of 56

Description

GPIO2_DEB[1:0]

GPIO2 input debounce time setting

GPIO2_DEB_RISE

GPIO2 input debounce rising edge enable

GPIO2_DEB_FALL

GPIO2 input debounce falling edge enable

4.3

Operating Modes

4.3.1

DA9131 is ON when the IC_EN port is higher than VIH_EN and the supply voltage is higher than

VTHR_POR. Once enabled, the host processor can start communicating with DA9131 using the control

interface, after the tIC_EN delay.

4.3.2

OFF

DA9131 is OFF when the IC_EN port is lower than VIL_EN. In OFF, the bucks are always disabled and

LX nodes are pulled down by (typically 150 Ω) internal pull-down resistors.

4.4

I2C Communication

All features of DA9131 can be controlled with the I2C interface which is enabled or disabled in

I2C_EN

Description

I2C disable: SCL/GPIO3 and SDA/GPIO4 pins can be used as GPIO

I2C enable: SCL/GPIO3 and SDA/GPIO4 pins are used as I2C clock input and I2C data

input/output.

GPIO3 functions as the I2C clock and GPIO4 carries all the power manager bidirectional I2C data.

The I2C interface is open-drain supporting multiple devices on a single line. The bus lines have to be

pulled high by external pull-up resistors (2

kΩ to 20 kΩ). The standard frequency of the I2C bus is

1 MHz in fast-mode plus (FM+), 400 kHz in fast-mode, or 100 kHz in standard mode.

4.4.1

I2C Protocol

All data is transmitted across the I2C bus in eight-bit groups. To send a bit, the SDA line is driven

towards the intended state while the SCL is low (a low SDA indicates a zero bit). Once the SDA has

settled, the SCL line is brought high and then low. This pulse on SCL clocks the SDA bit into the

receiver’s shift register.

A two-byte serial protocol is used containing one byte for address and one byte data. Data and

address transfer are transmitted MSB first for both read and write operations. All transmissions begin

with the START condition from the master while the bus is in idle state (the bus is free). It is initiated

by a high to low transition on the SDA line while the SCL is in the high state (a STOP condition is

indicated by a low to high transition on the SDA line while the SCL is in the high state).

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