SLG46880 datasheet(2/353 Pages) DIALOG

2 / 353 page

Datasheet

25-Feb-2021

CFR0011-120-00

Revision 3.12

2 of 353

SLG46880/81

GreenPAK Programmable Mixed-Signal Matrix with Asynchronous

State Machine and Dual Supply

Contents

General Description ................................................................................................................................................................. 1

Key Features............................................................................................................................................................................. 1

Applications.............................................................................................................................................................................. 1

1 Block Diagram ...................................................................................................................................................................... 9

2 Pinout ..................................................................................................................................................................................10

2.1 Pin Configuration - STQFN- 32L .........................................................................................................................10

3 Characteristics ...................................................................................................................................................................12

3.1 Absolute Maximum Ratings .................................................................................................................................12

3.2 Electrostatic Discharge Ratings ...........................................................................................................................12

3.3 Recommended Operating Conditions .................................................................................................................12

3.4 Electrical Characteristics ......................................................................................................................................13

3.5 Timing Characteristics ..........................................................................................................................................23

3.6 Oscillator Characteristics .....................................................................................................................................27

3.7 Analog Comparator Characteristics ....................................................................................................................29

3.8 Analog Temperature Sensor Characteristics .......................................................................................................31

4 User Programmability ........................................................................................................................................................34

5 IO Pins .................................................................................................................................................................................35

5.1 IO Pins .................................................................................................................................................................35

5.2 Pull-Up/Down Resistors .......................................................................................................................................35

5.3 100 ns Debounce Delay .......................................................................................................................................35

5.4 Fast Pull-up/down during Power-up .....................................................................................................................35

5.5 Digital Input Latch ................................................................................................................................................35

5.6 GPO Output Skew ................................................................................................................................................36

5.7 Ultra-Low Power Digital Input (SLG46881 only) ..................................................................................................36

5.8 GPI IO Structure (VDD) ........................................................................................................................................37

5.9 GPI with Input Latch IO Structure (VDD) .............................................................................................................39

5.10 GPI with I2C Mode IO Structure (VDD) ...............................................................................................................41

5.11 GPIO with Matrix OE IO Structure (VDD or VDD2) ..............................................................................................43

5.12 GPIO with Matrix OE and Input Latch IO Structure (VDD or VDD2) ....................................................................45

5.13 GPI with Input Latch and Crystal Input IO Structure (VDD) ................................................................................47

5.14 GPO Register OE IO Structure (VDD or VDD2) ...................................................................................................49

5.15 IO Typical Performance .....................................................................................................................................50

6 Connection Matrix ..............................................................................................................................................................53

6.1 Matrix Input Table ................................................................................................................................................54

6.2 Matrix Output Table .............................................................................................................................................55

6.3 Connection Matrix Virtual Inputs ..........................................................................................................................58

6.4 Connection Matrix Virtual Outputs .......................................................................................................................58

7 Combination Function Macrocells ....................................................................................................................................59

7.1 2-Bit LUT or D Flip-Flop Macrocells .....................................................................................................................59

7.2 2-bit LUT or Programmable Pattern Generator ....................................................................................................61

7.3 3-Bit LUT or D Flip-Flop with Set/Reset Macrocells .............................................................................................63

7.4 3-Bit LUT or Pipe Delay/Ripple Counter Macrocell ..............................................................................................69

7.5 3-Bit LUT or 8-Bit Counter/Delay Macrocells .......................................................................................................73

7.6 CNT/DLY/FSM Timing Diagrams .........................................................................................................................78

7.7 4-Bit LUT or 16-Bit Counter/Delay Macrocell .......................................................................................................87

7.8 Wake and Sleep Controller ..................................................................................................................................90

8 Analog Comparators ..........................................................................................................................................................95

8.1 ACMP0H Block Diagram .....................................................................................................................................96

8.2 ACMP1H Block Diagram .....................................................................................................................................97

8.3 ACMP2L Block Diagram .....................................................................................................................................98

8.4 ACMP3L Block Diagram .....................................................................................................................................99

8.5 ACMP Typical Performance ...............................................................................................................................100

9 Programmable Delay/Edge Detector .............................................................................................................................. 104

9.1 Programmable Delay Timing Diagram - Edge Detector Output ......................................................................... 104

10 Additional Logic Function ............................................................................................................................................. 105

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