(Preliminary)

PLL500-37

Low Phase Noise VCXO (36MHz to 130MHz)

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 03/01/06 Page 1

FEATURES

• VCXO output for the 36MHz to 130MHz range

• Low phase noise (-148 dBc @ 10kHz offset at

77.76MHz).

• CMOS output with OE tri-state control.

• 36 to 130MHz fundamental crystal input.

• Integrated high linearity variable capacitors.

• 8mA drive capability at TTL output.

• +/- 150 ppm pull range, max 5% linearity.

• Low jitter (RMS): 2.5ps period jitter.

• Single 2.5V ±10% or 3.3V ±10 power supply.

• Operating temperature range from -40°C to +85°C

• Available in Die or Wafer form.

DESCRIPTION

The PLL500-37 is a low cost, high performance and

low phase noise VCXO for the 36 to 130MHz range,

providing less than -148dBc at 10kHz offset at

77.76MHz. The very low jitter (2.5 ps RMS period

jitter) makes this chip ideal for applications requiring

voltage controlled frequency sources. Input crystal

can range from 36 to 130MHz (fundamental resonant

mode).

PIN AND PAD CONFIGURATION

Note: ^ denotes pull-up resistor

DIE SPECIFICATIONS

Name

Value

Size

39 x 32 mil

Reverse side

GND

Pad dimensions

80 micron x 80 micron

Thickness

12 mil

BLOCK DIAGRAM

XTAL

OSC

OE

XIN

XOUT

VCON

VARICAP

5

Y

X

(0,0)

(812,986)

32 mil

8

6

2

3

4

7

1XIN

OE^

CLK

GND

VCON

XOUT

OE^

VDD