(Preliminary)

PLL500-37

Low Phase Noise VCXO (36MHz to 130MHz)

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 03/01/06 Page 2

PAD ASSIGNMENT AND DESCRIPTION

Die Pad Position

Name

Pad #

X (

µm)

Y (

µm)

Type

Description

XIN

1

94.2

768.6

I

Crystal input pin.

2

94.2

605.0

OE

7

715.5

626.7

P

Output Enable input pin. Disables the output when low.

Internal pull-up enables output by default if pin is not

connected to low. Use only one OE signal.

VCON

3

94.2

331.7

I

Frequency control voltage input pin.

GND

4

94.2

140.4

P

Ground pin.

CLK

5

715.5

203.9

O

Output clock pin.

VDD

6

715.5

455.7

P

VDD power supply pin.

XOUT

8

477.0

888.8

O

Crystal output pin.

ELECTRICAL SPECIFICATIONS

1. Absolute Maximum Ratings

PARAMETERS

SYMBOL

MIN.

MAX.

UNITS

Supply Voltage

4.6

V

Input Voltage, dc

-0.5

V

Output Voltage, dc

-0.5

V

Storage Temperature

-65

150

°C

Ambient Operating Temperature*

-40

85

°C

Junction Temperature

125

°C

Lead Temperature (soldering, 10s)

260

°C

ESD Protection, Human Body Model

2

kV

Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the

device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other con-

ditions above the operational limits noted in this specification is not implied.

* Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only.