PCF8545ATT datasheet(35/51 Pages) NXP

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NXP Semiconductors

PCF8553

40 × 4 LCD segment driver

aaa-012364

128

160

256

512

768

1024

1280

1536

ffr (Hz)

fclk

(Hz)

(4)

(3)

(2)

(1)

1. nMUX = 1.

2. nMUX = 2.

3. nMUX = 3.

4. nMUX = 4.

Figure 25. Relation of frame frequency (ffr), clock frequency (fclk) and multiplex-rate (nMUX)

VDD = 1.8 V to 5.5 V; VSS = 0 V; Tamb = -40 °C to +85 °C; unless otherwise specified; all timing values are valid within the

operating supply voltage and Tamb range and are referenced to VIL and VIH with an input voltage swing of VSS to VDD. [1]

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Pin SCL

fSCL

SCL clock frequency

400

kHz

tLOW

LOW period of the SCL

clock

1.3

µs

tHIGH

HIGH period of the SCL

clock

0.6

µs

Pin SDA

tSU;DAT

data set-up time

100

tHD;DAT

data hold time

Pins SCL and SDA

tBUF

bus free time between

a STOP and START

condition

1.3

µs

tSU;STO

set-up time for STOP

condition

0.6

µs

tHD;STA

hold time (repeated)

START condition

0.6

µs

tSU;STA

set-up time for a repeated

START condition

0.6

µs

Table 19. I2C-bus characteristics

PCF8553

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Product data sheet

Rev. 4 — 20 April 2021

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