AT45DB161E datasheet(21/80 Pages) DIALOG

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AT45DB161E

DS-AT45DB161E–8782N–03-2021

7.10 Chip Erase

The Chip Erase command allows the entire main memory array to be erased can be erased at one time.

To execute the Chip Erase command, a four-byte command sequence of C7h, 94h, 80h, and 9Ah must be clocked

into the device. Since the entire memory array is to be erased, no address bytes need to be clocked into the

device, and any data clocked in after the opcode are ignored. After the last bit of the opcode sequence has been

clocked in, the CS pin must be deasserted to start the erase process. The erase operation is internally self-timed

and takes a time of tCE. During this time, the RDY/BUSY bit in the Status Register indicates that the device is busy.

The Chip Erase command does not affect sectors that are protected or locked down; the contents of those sectors

remains unchanged. Only those sectors that are not protected or locked down are erased.

The WP pin can be asserted while the device is erasing, but protection is not activated until the internal erase cycle

completes.

The device also incorporates an intelligent algorithm that can detect when a byte location fails to erase properly. If

an erase error arises, it is indicated by the EPE bit in the Status Register.

Table 7-3.

Chip Erase Command

Figure 7-1. Chip Erase

7.11 Program/Erase Suspend

In some code and data storage applications, it might not be possible for the system to wait the milliseconds

required for the Flash memory to complete a program or erase cycle. The Program/Erase Suspend command

allows a program or erase operation in progress to a particular 128-kB sector of the main memory array to be

suspended so that other device operations can be performed.

Example:

By suspending an erase operation to a particular sector, the system can perform functions such as a

program or read operation within a different 128-kB sector. Other device operations, such as Read Status

To perform a Program/Erase Suspend, an opcode of B0h must be clocked into the device. No address bytes need

to be clocked into the device, and any data clocked in after the opcode are ignored. When the CS pin is

deasserted, the program or erase operation currently in progress is suspended within a time of tSUSP. One of the

Program Suspend bits (PS1 or PS2) or the Erase Suspend bit (ES) in the Status Register is then set to the logic 1

state. Also, the RDY/BUSY bit in the Status Register indicates that the device is ready for another operation.

Read operations are not allowed to a 128-kB sector that has had its program or erase operation suspended. If a

read is attempted to a suspended sector, then the device outputs undefined data. Therefore, when performing a

Continuous Array Read operation and the device's internal address counter increments and crosses the sector

boundary to a suspended sector, the device then starts outputting undefined data continuously until the address

counter increments and crosses a sector boundary to an unsuspended sector.

Command

Byte 1

Byte 2

Byte 3

Byte 4

Chip Erase

C7h

94h

80h

9Ah

C7h

94h

80h

9Ah

Each transition represents eight bits

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