AT45DB161E datasheet(39/80 Pages) DIALOG

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AT45DB161E

DS-AT45DB161E–8782N–03-2021

11.1 Resume from Deep Power-Down

In order to exit the Deep Power-Down mode and resume normal device operation, the Resume from Deep Power-

Down command must be issued. The Resume from Deep Power-Down command is the only command that the

device recognizes while in the Deep Power-Down mode.

To resume from the Deep Power-Down mode, the CS pin must first be asserted and then the opcode ABh must be

clocked into the device. Any additional data clocked into the device after the opcode is ignored. When the CS pin is

deasserted, the device exits the Deep Power-Down mode and return to the standby mode within the maximum

time of tRDPD. After the device has returned to the standby mode, normal command operations such as Continuous

Array Read can be resumed.

If the complete opcode is not clocked in before the CS pin is deasserted, or if the CS pin is not deasserted on an

even byte boundary (multiples of eight bits), then the device aborts the operation and return to the Deep Power-

Down mode.

Figure 11-2. Resume from Deep Power-Down Timing

11.2 Ultra-Deep Power-Down

The Ultra-Deep Power-Down mode allows the device to consume far less power compared to the standby and

Deep Power-Down modes by shutting down additional internal circuitry. Since almost all active circuitry is

shutdown in this mode to conserve power, the contents of the SRAM buffers cannot be maintained. Therefore, any

data stored in the SRAM buffers is lost once the device enters the Ultra-Deep Power-Down mode.

When the device is in the Ultra-Deep Power-Down mode, all commands including the Status Register Read and

Resume from Deep Power-Down commands are ignored. Since all commands are ignored, the mode can be used

as an extra protection mechanism against program and erase operations.

Entering the Ultra-Deep Power-Down mode is done by asserting the CS pin, clocking in the opcode 79h, and then

deasserting the CS pin. Any additional data clocked into the device after the opcode is ignored. When the CS pin is

deasserted, the device enters the Ultra-Deep Power-Down mode within the maximum time of tEUDPD.

The complete opcode must be clocked in before the CS pin is deasserted, and the CS pin must be deasserted on

an even byte boundary (multiples of eight bits); otherwise, the device aborts the operation and return to the

standby mode once the CS pin is deasserted. Also, the device defaults to the standby mode after a power cycle.

SCK

MSB

ICC

10101011

Opcode

High-impedance

Deep Power-Down Mode Current

Active Current

Standby Mode Current

tRDPD

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