AT25SL641 datasheet(37/76 Pages) DIALOG

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AT25SL641

DS-25SL641–113F–12/2018

7.20

Chip Erase (C7h / 60h)

The Chip Erase instruction clears all bits in the device to FFh (all 1s). Prior to the Chip Erase Instruction, a Write Enable

instruction must be issued. The instruction is initiated by driving the CS pin low and shifting the instruction code C7h or

60h. Please refer to Figure 7-31.

The CS pin must go high after the eighth bit of the last byte has been latched in, otherwise, the Chip Erase instruction

will not be executed. After CS is driven high, the self-timed Chip Erase instruction commences for a duration of t

CE (See

AC Characteristics).

While the Chip Erase cycle is in progress, the Read Status Register instruction may still be accessed to check the status

of the BUSY bit. The BUSY bit is a 1 during the Chip Erase cycle and becomes a 0 when the cycle is finished and the

device is ready to accept other instructions. When the BUSY bit is asserted, the Write Enable Latch (WEL) bit in the

Status Register is cleared to 0.

Figure 7-31. Chip Erase Instruction for SPI Mode (left) and QPI Mode (right)

7.21

Erase / Program Suspend (75h)

The Erase/Program Suspend instruction allows the system to interrupt a Block Erase, Block Erase operation or a

Page Program, Quad Data Input Page Program, Quad Page Program operation.

Erase Suspend is valid only during a Block Erase operation. The Write Status Register-1 (01h), Write Status Register-2

(31h) instruction and Erase instructions (20h, 52h, D8h, C7h, 60h) are not allowed during an Erase Suspend. During the

Chip Erase operation, the Erase Suspend instruction is ignored.

Program Suspend is valid only during the Page Program, Quad Data Input Page Program or Quad Page Program

operation. The Write Status Register-1 (01h), Write Status Register-2 (31h) instruction, Program instructions (02h and

33h) and Erase Instructions (20h, 52h, D8h, C7h, 60h) are not allowed during Program Suspend.

The Erase/Program Suspend instruction 75h is accepted by the device only if the SUS bit in the Status Register equals

to 0 and the BUSY bit equals to 1 while a Block Erase or a Page Program operation is on-going. If the SUS bit equals

to 1 or the BUSY bit equals to 0, the Suspend instruction is ignored by the device. A maximum of time of t

SUS (See AC

Characteristics) is required to suspend the erase or program operation.

After executing the Erase/Program Suspend, the SUS bit in the Status Register is toggled from 0 to 1 immediately. The

BUSY bit in the Status Register is cleared from 1 to 0 within t

SUS. For a previously resumed Erase/Program operation, it

is also required that the Suspend instruction 75h is not issued earlier than a minimum of time of t

SUS following the

preceding Resume instruction 7Ah.

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