Preliminary

PLL520-70

CMOS Low Phase Noise VCXO (for 45-90MHz Fund Xtal)

47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991

Rev 8/26/02 Page 4

PAD ASSIGNMENT

Pad #

Name

X (

µµm)

Y (

µµm)

1

Optional GND

248

109

2

Optional GND

361

109

3

Optional GND

473

109

4

Optional GND

587

109

5

GND

702

109

6

Reserved

874

109

7

Optional GNDBUF

1042

109

8

Optional GNDBUF

1171

109

9

Not connected

1400

125

10

Not connected

1400

259

11

CMOS OUT

1400

476

12

VDDBUF

1400

616

13

Optional VDDBUF

1400

716

14

Not connected

1400

871

15

Not connected

1400

1089

16

Optional CMOS OUT

1400

1227

17

GNDBUF

1389

1365

18

Reserved

1232

1365

19

DRIVE_SEL

1042

1365

20

Not connected

854

1365

21

Optional VDD

659

1365

22

Optional VDD

559

1365

23

VDD

459

1365

24

Optional VDD

358

1365

25

Not connected

194

1365

26

XIN

109

1223

27

XOUT

109

1017

28

Not connected

109

858

29

Not connected

109

646

30

OE_CTRL

109

397

31

VCON

109

181

Note: for optimal Phase Noise performance, it is recommended to bond all optional VDD and GND pads.