Preliminary

PLL520-70

CMOS Low Phase Noise VCXO (for 45-90MHz Fund Xtal)

47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991

Rev 8/26/02 Page 3

4. General Electrical Specifications

PARAMETERS

SYMBOL

CONDITIONS

MIN.

TYP.

MAX.

UNITS

Supply Current (Loaded Outputs)

40

mA

Operating Voltage

3.13

3.47

V

Output Clock Duty Cycle

@ 1.4V

45

50

55

%

Short Circuit Current

±50

mA

5. Jitter specifications

PARAMETERS

CONDITIONS

MIN.

TYP.

MAX.

UNITS

Period jitter RMS

77.76MHz

3.5*

ps

Period jitter peak-to-peak

77.76MHz

24*

ps

Integrated jitter RMS

Integrated 12 kHz to 20 MHz at 77.76MHz

0.5*

ps

*: To be measured

6. Phase noise specifications

PARAMETERS

FREQUENCY

@10Hz

@100Hz

@1kHz

@10kHz

@100kHz

UNITS

Phase Noise relative to

carrier

77.76MHz

-75

-95

-125

-145

-155

dBc/Hz

Note: Phase Noise at VCON = 0V – to be measured

7. CMOS Output Electrical Specifications

PARAMETERS

SYMBOL

CONDITIONS

MIN.

TYP.

MAX.

UNITS

Output High Voltage

2.4

V

Output Low Voltage

0.4

V

Output High Voltage at CMOS level

V

At TTL level (High drive)

36

51

mA

Output drive current

At TTL level (Standard drive)

12

17

mA

8. CMOS Switching Characteristics

PARAMETERS

SYMBOL

CONDITIONS

MIN.

TYP.

MAX.

UNITS

0.8V ~ 2.0V with 10 pF load

1.15

Output Clock Rise/Fall Time

(Standard Drive)

0.3V ~ 3.0V with 15 pF load

3.7

0.8V ~ 2.0V with 10 pF load

0.5

Output Clock Rise/Fall Time

(High Drive)

0.3V ~ 3.0V with 15 pF load

1.5

ns