Preliminary

PLL103-07

2 DIMM DDR Fanout Buffer

47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991

Rev 01/03/01 Page 1

FEATURES

• Generates 12-output buffers from one input.

• Supports VIA Pro266 DDR chipset.

• Supports up to 2 DDR DIMMS.

• Supports up to 400MHz DDR, SDRAMS.

• One additional output for feedback.

• 6 differential clock distribution.

• Less than 5ns delay.

• Skew between any outputs is less than 100 ps.

• 2.5V Supply range.

• Available in 28-pin SSOP.

BLOCK DIAGRAM

PIN CONFIGURATION

Note: #: Active Low

DESCRIPTIONS

The PLL103-07 is designed as a 2.5V buffer to

distribute high-speed clocks in PC applications. The

device has 12 outputs. These outputs can be

configured to support 2 DDR DIMMs. The PLL103-07

can be used in conjunction with the PLL202-04 or

similar clock synthesizer for the VIA Pro 266 chipset.

28

26

25

24

23

1

2

3

4

5

6

7

8

9

10

11

12

DDRC2

VDD2.5

GND

FBOUT

13

14

VDD2.5

DDRT0

DDRC0

GND

DDRT1

DDRC1

VDD2.5

BUF_IN

GND

DDRT2

27

22

21

20

19

18

17

16

15

SCLK

GND

DDRT5

GND

SDATA

DDRC5

VDD2.5

DDRT4

DDRC4

VDD2.5

GND

DDRT3

DDRC3

VDD2.5

BUF_IN

SDATA

SCLK

I2C

Control

DDR0T

DDR0C

DDR1T

DDR1C

DDR2T

DDR2C

DDR3T

DDR3C

DDR4T

DDR4C

DDR5T

DDR5C

FBOUT