Preliminary

PLL103-07

2 DIMM DDR Fanout Buffer

47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991

Rev 01/03/01 Page 2

PIN DESCRIPTIONS

Name

Number

Type

Description

FBOUT

1

O

Feedback clock for chipset.

BUF_IN

10

I

Reference input from chipset.

DDRT[0:5]

3,7,12,19,

23,27

O

“True” clocks of differential pair outputs.

DDRC[0:5]

4,8,13,18,

22,26

O

“Complementary” clocks of differential pair outputs.

VDD2.5

5,9,14,

17,21,25

P

2.5V power supply.

GND

6,11,20,24

P

Ground.