The 68HC16 uses a phase-locked loop (PLL) to set its

bus speed. Crystal Y1 is a 32.768kHz frequency refer-

ence. The internal oscillator runs 256 times faster than

the external crystal. When the 68HC16 is reset, it waits

for the PLL to lock before it executes any software. After

the PLL locks onto the reference frequency, the soft-

ware doubles the clock speed by writing to the clock

synthesizer control register, selecting a bus speed of

16.78MHz.

U5, the user RAM area, is a 32kbyte CMOS static RAM.

The 74HCT245 octal buffer lets the 68HC16 module

access an 8-bit port on the 40-pin interface connector.

This memory-mapped port consists of separate read

and write strobes, four chip selects, four address LSBs,

and eight data bits.

Serial Communications

J3 is an RS-232 serial port, designed to be compatible

with the IBM PC 9-pin serial port. Use a straight-through

DB9 male-to-female cable to connect J3 to this port. If

the only available serial port has a 25-pin connector,

you may use a standard 25-pin to 9-pin adapter. Table

9 shows the pinout of J3.

The MAX233 is an RS-232 interface voltage level shifter

with two transmitters and two receivers. It includes a

built-in charge pump with internal capacitors that gen-

erates the output voltages necessary to drive RS-232

lines.

40-Pin Data Connector J1

The 20 x 2 pin header connects the 68HC16 module to

a Maxim EV kit. Table 10 lists the function of each pin.

Note that 68HC16 object code is not compatible with

68HC11 object code. Use the 68HC16 module only

with those modules that are designed to support it, and

only download code that is targeted for the 68HC16

module. Downloading incorrect object code into the

68HC16 module will have unpredictable results.

Address Ranges

The 68HC16 µC generates various enable signals for

different address ranges. The ROM and RAM enable

signals are fed directly to the respective chips. Several

additional signals (J1.11–J1.14) are available on the

data connector to be used by Maxim EV kits. Table 11

outlines the address ranges for each of the elements

found on the 68HC16 module, and Table 12 is a truth

table that describes the logic for each of the 68HC16’s

chip-select outputs. Because the addresses are not

completely decoded, the boot ROM and user RAM

have shadows.

MAX194 Evaluation System/Evaluation Kit

16

______________________________________________________________________________________

Table 9. Serial Communications Port J3

Unused

None

9

Handshake; hard-wired to RTS

CTS

8

Handshake; hard-wired to CTS

RTS

7

Handshake; hard-wired to DCD and DTR

DSR

6

Signal ground connection

GND

5

Handshake; hard-wired to DCD and DSR

DTR

4

RS-232-compatible data input to

68HC16 module

TXD

3

Handshake; hard-wired to DTR and DSR

DCD

1

FUNCTION

NAME

PIN

RS-232-compatible data output from

68HC16 module

RXD

2

Table 10. 40-Pin Data-Connector Signals

General I/O port bit 7

IC4

34

General I/O port bit 0 (LSB)

IC1

27

Buffered data bus bits 1–7

EXTD1–7

20–26

Unregulated input voltage

VPREREG

5, 6

Buffered data bus 0 (LSB)

EXTD0

19

Read strobe

RD

9

Ground

GND

1–4

FUNCTION

NAME

PIN

Address bit 2

A02

17

+5V from on-board regulator

VCC

7, 8

Chip select for 7E000–7E7FF

7E000

11

Chip select for 7F000–7F7FF

7F000

13

Write strobe

WR

10

Chip select for 7E800–7EFFF

7E800

12

Address bit 0 (LSB)

A00

15

Chip select for 7F800–7FFFF

7F800

14

Pulse-width-modulator output

PWMA

40

QSPI chip-select output

PCS0/SS

38

QSPI serial clock

SCK

37

QSPI master-out, slave-in

MOSI

36

QSPI master-in, slave-out

MISO

35

Address bit 1

A01

16

Address bit 3

A03

18

General I/O port bit 1

IC2

28

General I/O port bit 2

IC3

29

General I/O port bit 3

OC1

30

General I/O port bit 4

OC2

31

General I/O port bit 5

OC3

32

General I/O port bit 6

OC4

33

System clock output

CLKOUT

39