Analog Input Buffer

The analog input to the MAX194 may be buffered by

feedback circuit consists of four passive components:

R41, R61, C171, and R51. R41 isolates the op-amp’s

output from the dynamic capacitive load at the AIN

input. R61 makes the network accurate at the reference

input (without R61, the reference voltage would appear

at the output of the op amp). C171 compensates the

high-frequency response by making R51 dominate at

high frequencies.

Input offset may be improved by adding a 1000pF to

0.01µF ceramic capacitor at site C28.

Voltage Reference

The voltage reference U2 provides a 4.096V reference,

which is buffered by U5. The buffer isolates the refer-

ence from the MAX194’s capacitive switching load. To

eliminate the buffer circuit, cut traces JU8 and JU9 and

connect a wire from JU9 pin 1 to the VREF pad.

Reference Buffer

The reference input to the MAX194 may be buffered by

U5. The MAX400 op amp is used because of its low

amp, the substrate can be connected to the quiet ana-

log ground, reducing the noise coupled through the

power supplies. The feedback circuit consists of four

passive components: R4, R6, C17, and R5. R4 isolates

the op-amp’s output from the heavy capacitive load

that bypasses the VREF pin. R6 makes the network

accurate at the reference input (without R6, the refer-

ence voltage would appear at the output of the op

amp). C17 compensates the high-frequency response

by making R5 dominate at high frequencies.

The reference buffer U5 draws its power through the

lowpass filter formed by R3 and C18. The filter provides

the necessary power-supply rejection. U5 is powered

by the unregulated input supply to ensure enough

headroom to buffer the 4.096V reference.

Layout, Power Supplies, and Grounding

Good PC board layout necessary to achieve specified

performance, and an analog ground plane is essential

for optimum performance. The PC board layout artist

must be provided with explicit instructions, preferably a

pencil sketch of the placement of sensitive analog com-

ponents and the routing of ground connections. See

the EV kit PC board layout for an example. Use the fol-

lowing guidelines:

1) At the schematic level, keep the analog power sup-

plies and grounds separate from all other power

supplies and grounds. Digital power may be con-

nected to analog power through a 10

Ω series resis-

tor to attenuate digital noise.

2) Cluster the MAX194, the voltage reference, and any

input or reference buffers near the site where the

analog signal enters the board. Place 0.1µF ceramic

decoupling capacitors within 10mm of the MAX194’s

power-supply and voltage-reference pins.

3) Keep the analog-input signal ground return sepa-

rate from the analog ground plane, connecting to

analog ground only at the AGND pin of the

MAX194. The analog input and its signal ground-

return traces should both follow the same route to

help reject common-mode noise.

MAX194 Evaluation System/Evaluation Kit

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7

Table 7. Data-Interface Connections

PIN NO.

68HC16 SIGNAL

MAX194 SIGNAL

FUNCTION

1–4

GND

GND

Ground

5, 6

+12V

+12V

Unregulated 12V DC Supply

7, 8

+5V

VDDD

Regulated +5V DC from 68HC16 Module

9–26

Reserved

Reserved

Reserved

27

IC1

EOC

End-of-Conversion Output from MAX194

28, 29, 30

Reserved

Reserved

Reserved

31

OC2

RESET

Active-Low RESET to MAX194

32

OC3

BP/UP/SHDN

Shutdown/Bipolar/Unipolar Input to MAX194

33, 34

Reserved

Reserved

Reserved

35

MISO

DOUT

QSPI Master Input; Serial Data Output from MAX194

36

Reserved

Reserved

Reserved

37

SCK

CLK

QSPI Serial Clock from 68HC16

38

PCS0

CS

QSPI Chip-Select from 68HC16

39, 40

Reserved

Reserved

Reserved