LM25005 datasheet(16/21 Pages) NSC

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Application Information (Continued)

When the buck switch turns on, the current into the VIN pin

steps to the lower peak of the inductor current waveform,

ramps up to the peak value, then drops to zero at turn-off.

The average current into VIN during the on-time is the load

current. The input capacitance should be selected for RMS

current rating and minimum ripple voltage. A good approxi-

mation for the required ripple current rating necessary is

RMS > IOUT /2.

Quality ceramic capacitors with a low ESR should be se-

lected for the input filter. To allow for capacitor tolerances

and voltage effects, two 2.2 µF, 100V ceramic capacitors will

be used. If step input voltage transients are expected near

the maximum rating of the LM25005, a careful evaluation of

ringing and possible spikes at the device VIN pin should be

completed. An additional damping network or input voltage

clamp may be required in these cases.

The capacitor at the VCC pin provides noise filtering and

stability for the V

CC regulator. The recommended value of C8

should be no smaller than 0.1 µF, and should be a good

quality, low ESR, ceramic capacitor. A value of 0.47 µF was

selected for this design.

The bootstrap capacitor between the BST and the SW pins

supplies the gate current to charge the buck switch gate at

turn-on. The recommended value of C7 is 0.022 µF, and

should be a good quality, low ESR, ceramic capacitor.

The capacitor at the SS pin determines the soft-start time,

i.e. the time for the reference voltage and the output voltage,

to reach the final regulated value. The time is determined

from:

For this application, a C4 value of 0.01 µF was chosen which

corresponds to a soft-start time of 1 ms.

R5, R6

R5 and R6 set the output voltage level, the ratio of these

resistors is calculated from:

R5/R6 = (V

OUT / 1.225V) - 1

For a 5V output, the R5/R6 ratio calculates to 3.082. The

resistors should be chosen from standard value resistors, a

good starting point is selection in the range of 1.0 k

Ω -10kΩ.

Values of 5.11 k

Ω for R5, and 1.65 kΩ for R6 were selected.

R1, R2, C12

A voltage divider can be connected to the SD pin to set a

minimum operating voltage Vin

(min) for the regulator. If this

feature is required, the easiest approach to select the divider

resistor values is to select a value for R1 (between 10 k

Ω

and 100 k

Ω recommended) then calculate R2 from:

Capacitor C12 provides filtering for the divider. The voltage

at the SD pin should never exceed 8V, when using an

external set-point divider it may be necessary to clamp the

SD pin at high input voltage conditions. The reference de-

sign utilizes the full range of the LM25005 (7V to 42V);

therefore these components can be omitted. With the SD pin

open circuit the LM25005 responds once the Vcc UVLO

threshold is satisfied.

R7, C11

A snubber network across the power diode reduces ringing

and spikes at the switching node. Excessive ringing and

spikes can cause erratic operation and couple spikes and

noise to the output. In the limit, spikes beyond the rating of

the LM25005 or the re-circulating diode can damage these

devices. Selecting the values for the snubber is best accom-

plished through empirical methods. First, make sure the lead

lengths for the snubber connections are very short. For the

current levels typical for the LM25005 a resistor value be-

tween 5 and 20 Ohms is adequate. Increasing the value of

the snubber capacitor results in more damping but higher

losses. Select a minimum value of C11 that provides ad-

equate damping of the SW pin waveform at high load.

R4, C5, C6

These components configure the error amplifier gain char-

acteristics to accomplish a stable overall loop gain. One

advantage of current mode control is the ability to close the

loop with only two feedback components, R4 and C5. The

overall loop gain is the product of the modulator gain and the

error amplifier gain. The DC modulator gain of the LM25005

is as follows:

DC Gain

(MOD) =Gm(MOD) xRLOAD =2xRLOAD

The dominant low frequency pole of the modulator is deter-

mined by the load resistance (R

LOAD,) and output capaci-

tance (C

OUT). The corner frequency of this pole is:

p(MOD) =1/(2

π R

LOAD COUT)

For R

LOAD =5

Ω and C

OUT = 177 µF then fp(MOD) = 180Hz

DC Gain

(MOD) =2x5=10=20dB

For the design example of Figure 1 the following modulator

gain vs. frequency characteristic was measured as shown in

Figure 8.

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