LM25005 datasheet(11/21 Pages) NSC

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Shutdown / Standby

The LM25005 contains a dual level Shutdown (SD) circuit.

When the SD pin voltage is below 0.7V, the regulator is in a

low current shutdown mode. When the SD pin voltage is

greater than 0.7V but less than 1.225V, the regulator is in

standby mode. In standby mode the Vcc regulator is active

but the output switch is disabled. When the SD pin voltage

exceeds 1.225V, the output switch is enabled and normal

operation begins. An internal 5µA pull-up current source

configures the regulator to be fully operational if the SD pin is

left open.

An external set-point voltage divider from Vin to GND can be

used to set the operational input range of the regulator. The

divider must be designed such that the voltage at the SD pin

will be greater than 1.225V when Vin is in the desired

operating range. The internal 5µA pull-up current source

must be included in calculations of the external set-point

divider. Hysteresis of 0.1V is included for both the shutdown

and standby thresholds. The voltage at the SD pin should

never exceed 8V. When using an external set-point divider, it

may be necessary to clamp the SD pin to limit its voltage at

high input voltage conditions.

The SD pin can also be used to implement various remote

enable / disable functions. Pulling the UVLO pin below the

0.7V threshold totally disables the controller. If the SD pin

voltage is above 1.225V the regulator will be operational.

Oscillator and Sync Capability

The LM25005 oscillator frequency is set by a single external

resistor connected between the RT pin and the AGND pin.

The R

T resistor should be located very close to the device

and connected directly to the pins of the IC (RT and

AGND).To set a desired oscillator frequency (F), the neces-

sary value for the R

T resistor can be calculated from the

following equation:

The SYNC pin can be used to synchronize the internal

oscillator to an external clock. The external clock must be of

higher frequency than the free-running frequency set by

the R

T resistor. A clock circuit with an open drain output is the

recommended interface from the external clock to the SYNC

pin. The clock pulse duration should be greater than 15 ns.

Multiple LM25005 and/or LM5005 devices can be synchro-

nized together simply by connecting the SYNC pins together.

In this configuration all of the devices will be synchronized to

the highest frequency device. The diagram in Figure 5 illus-

trates the SYNC input/output features of the LM25005. The

internal oscillator circuit drives the SYNC pin with a strong

pull-down / weak pull-up inverter. When the SYNC pin is

pulled low either by the internal oscillator or an external

clock, the ramp cycle of the oscillator is terminated and a

new oscillator cycle begins. Thus, if the SYNC pins of sev-

eral LM25005 IC’s are connected together, the IC with the

highest internal clock frequency will pull the connected

SYNC pins low first and terminate the oscillator ramp cycles

of the other IC’s. The LM25005 or LM5005 with the highest

programmed clock frequency will serve as the master and

control the switching frequency of the all the devices with

lower oscillator frequency.

20170005

FIGURE 3. Sync from External Clock

20170006

FIGURE 4. Sync from Multiple Devices

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