THS1007

SLAS286A – AUGUST 2000– REVISED DECEMBER 2002

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27

Write Timing (using WR, WR-controlled)

Figure 35 shows the write-timing behavior when the WR(R/W) input is programmed as a write input WR only. The

input RD acts as the read input in this configuration. This timing is called WR-controlled because WR is the last

external signal of CS0, CS1, and WR which becomes valid.

90%

90%

10%

tsu

th

D(0–9)

DATA_AV

10%

tw(WR)

tsu(CS)

th(CS)

CS0

CS1

WR

RD

Figure 35. Write Timing Diagram Using WR (WR-controlled)

Write Timing Parameter Using WR (WR-controlled)

PARAMETER

MIN

TYP

MAX

UNIT

tsu(CS)

Setup time, CS stable to last WR valid

0

ns

tsu

Setup time, data valid to first WR invalid

5

ns

th

Hold time, WR invalid to data invalid

2

ns

th(CS)

Hold time, WR invalid to CS change

5

ns

tw(WR)

Pulse duration, WR active

10

ns