THS1007

SLAS286A – AUGUST 2000– REVISED DECEMBER 2002

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26

Read Timing (using RD, RD-controlled)

Figure 34 shows the read-timing behavior when the WR(R/W) input is programmed as a write-input only. The input

RD acts as the read-input in this configuration. This timing is called RD-controlled because RD is the last external

signal of CS0, CS1, and RD which becomes valid.

90%

90%

90%

10%

tw(RD)

tsu(CS)

th(CS)

ta

th

td(CSDAV)

CS0

CS1

WR

RD

D(0–9)

DATA_AV

10%

Figure 34. Read Timing Diagram Using RD (RD-controlled)

Read Timing Parameter (RD-controlled)

PARAMETER

MIN

TYP

MAX

UNIT

tsu(CS)

Setup time, RD low to last CS valid

0

ns

ta

Access time, last CS valid to data valid

0

10

ns

td(CSDAV) Delay time, last CS valid to DATA_AV inactive

12

ns

th

Hold time, first CS invalid to data invalid

0

5

ns

th(CS)

Hold time, RD change to first CS invalid

5

ns

tw(RD)

Pulse duration, RD active

10

ns