3.2

Pin Descriptions

The following table describes the functional pins of the PD69208T4, PD69208M, and PD69204T4 Managers.

Table 3-1. Pin Descriptions

Pin

Designator

Type

Description

EPAD

Exposed PAD. Connect to analog ground. GND

must have sufficient copper mass on bottom or

top layer to ensure adequate thermal

performance.

1,18,45

N.C.

N/A

Not connected. Leave floating.

2

TST

Digital input

Test pin for production use only. Connect to

DGND.

3,4

VPORT_NEG0

Analog I/O

Negative port 0 output.

5,8,11,

14,16,

26,27,

29,32,

35,38

RESERVED

N/A

Reserved pin. Do not connect externally.

6,7

VPORT_NEG1

Analog I/O

Negative port 1 output.

9,10

VPORT_NEG2

Analog I/O

Negative port 2 output.

12,13

VPORT_NEG3

Analog I/O

Negative port 3 output.

15,21,28

AGND

Power

Analog ground.

17

VMAIN

Power

Main high voltage supply voltage. A low ESR 1 µF

(or higher) bypass capacitor, connected to AGND,

should be placed as close as possible to this pin

through low resistance traces.

19

DRV_VAUX5

Power

Driven outputs for 5 V external regulation; if

internal regulation is used, connect to pin 20. If an

external NPN is used to regulate the voltage,

connect this pin to Base and connect 4.7 µF

capacitor between this pin and AGND.

20

VAUX5

Power

Powered by regulated 5 V. Connect 4.7 µF or

higher capacitor between this pin and AGND. If an

external NPN is used to regulate the voltage,

connect this pin to the emitter. The collector

22

VAUX3P3

Power

Powered by regulated 3.3 V. A 4.7 µF or higher

filtering capacitor should be connected between

this pin and AGND. When an external 3.3 V

regulator is used, connect it to this pin to supply

the chip.

23

VAUX3P3_INT

Power

regulator is used. Leave unconnected (Floating) if

external 3.3 V regulator is used.

PD69208T4/PD69204T4/PD69208M

Pins

Datasheet

DS00003428C-page 14