3.2

Pin Descriptions

The following tables describe the functional pin descriptions of the PD39210 device.

Table 3-1. Pin Descriptions

PD39210

Pin

Designation

Type

Description

1

Reserved

OUT

Reserved UART. Leave open.

2

Reserved

IN

Reserved UART. Pull up to 3.3 V via 10 kΩ.

3

xSys_OK/LED System OK

OUT

System validity indication. The behavior of this output

is controlled by individual software mask. (Active

Low)

4

xDISABLE_PORTS

IN

Disable all PoE ports. When this input is asserted low,

the controller shuts down all PoE ports in the system.

See AN3361 for pin connection requirements. (Active

Low)

5

ESPI_MISO

IN

ESPI bus to PoE manager. SPI host in, client out. SPI

packets are received on this line.

6

ESPI_SCK

OUT

ESPI bus to PoE manager. SPI clock output to

PD39208, and LED stream clock output, set to 1

MHz.

7

ESPI_xCS

OUT

ESPI bus to PoE manager. SPI chip select. Pull-up

required. See AN3361 for pin connection

requirements. (Active Low)

8

ESPI_MOSI

OUT

ESPI bus from PoE manager. SPI host out, client in.

SPI packets are received on this line.

9

VDDA

Supply

Main Supply 3.3 V.

10

VSSA

GND

Ground.

11

Reserved

Analog_IN

Reserved Analog_IN. Connect to 3.3 V through 10 kΩ

or GND through 10 kΩ.

12, 19

Reserved

Reserved. Leave open.

13

I2C_ADDR_MEAS

Analog_IN

operation.

14

Reserved

Connect to GND.

15

UART0_TX

OUT

UART transmit to host. 15-byte protocol reply/

telemetry is transmitted on this line. The baud rate is

set to 19,200 bps.

16

UART0_RX

IN

UART receive from a host. 15-byte protocol

commands are received on this line. The baud rate is

set to 19,200 bps. Pull-up is required. See AN3361

for details.

17

Reserved

Oscillator

Reserved. Oscillator output. Leave open.

18

xLED_OE

OUT

Output enable signal for the LED stream. (Active

Low)

PD39210

Pins

Datasheet

DS00003554C-page 9