STW8019 datasheet(28/55 Pages) STMICROELECTRONICS

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Control registers

STw8009/STw8019

28/55

fieldct[2:0]: Digital field identification number

000 = indicates field 1

...

111 = indicates field 8

fieldct[0] also represents the odd/even information (odd=’0’, even=’1’)

jump: indicates whether a frame length modification has been programmed at ‘1’ from

programming of bit’ jump’ to end of frame(s) concerned.

(*)default = 0

Refer to register 6 and registers 21-22-23

These registers contain the 24-bit increment used by the DDFS if bit ‘selrst_inc’ equals ‘1’ to

generate the subcarrier phase i.e. the address that is supplied to the sine ROM. It therefore

allows to customize the subcarrier synthesized frequency.

1 LSB ~ 1.609325 Hz

The procedure to validate the usage of these registers rather than the hard-wired values is

the following:

- Load the registers with the required value

- Set bit ‘selrst_inc’ to 1 (Reg 5)

- Perform a software reset (Reg 6)

Note:

The values loaded in Reg10-12 are taken into account after a software reset, and ONLY IF

bit ‘selrst_inc’=’1’ (Reg. 5).

These registers are never reset and must be explicitly written into to contain sensible

information.

On hardware or on software reset with selrst_inc=’0’, the DDFS is initialized with a

hardwired increment, independent of Registers 10-12. These hardwired values being out of

any user register cannot be read.

These values are:

REGISTERS 10, 11, 12 Increment_dfs

Address:

0x000A to 0x000C

Type: R/W

register_10

d23

d22

d21

d20

d19

d18

d17

d16

register_11

d15

d14

d13

d12

d11

d10

register_12

Value

Frequency synthesized

d(23:0): 21F07C hexa for NTSC M

f=3.5795452 MHz

d(23:0): 2A098B hexa for PAL B,G,H,I,N

=4.43361875MHz

d(23:0): 21F694 hexa for PAL N

f=3.5820558 MHz

d(23:0): 21E6F0 hexa for PAL M

f=3.57561149 MHz

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