SH7705 datasheet(49/739 Pages) RENESAS

49 / 739 page

Rev. 2.00, 09/03, page 3 of 690

Item

Features

Bus state

controller (BSC)

• Physical address space is divided into eight areas: area 0, areas 2 to 4;

each a maximum of 64 Mbytes, and areas 5A, 5B, 6A, 6B; each a maximum

of 32 Mbytes

• The following features are settable for each area

Bus size (8, 16, or 32 bits). The supported bus size differs for each area.

Number of access wait cycles (Numbers of wait-state cycles during reading

and writing are independently selectable for some areas.)

Setting of idle wait cycles (for the same area or different area)

Specifying the memory type to be connected to each area enables direct

connection to SRAM, byte selection SRAM, SDRAM, and burst ROM. Some

areas support address/data multiplex I/O (MPX).

Outputs chip select signal (

CS0, CS2 to CS4, CS5A/B, CS6A/B)for

corresponding area (Programs are used to select the

CS assert/negate

timing.)

• SDRAM refresh function

Supports auto-refresh and self-refresh modes

• SDRAM burst access function

Different SDRAM can be connected to area 2 or area 3 (size/latency)

• Usable as either big or little endian machine

Direct memory

access controller

(DMAC)

• Four channels. Two of these channels support external requests.

• Burst mode and cycle steal mode

• Outputs transfer end signal in channel with DREQ (one channel)

• Supports intermittent mode (supports 16 or 64 cycles)

Clock pulse

generator (CPG)

• Clock mode: Input clock can be selected from external input (EXTAL or

CKIO) or crystal resonator

• Three types of clocks generated

CPU clock: max. 133.34 MHz/100 MHz

Bus clock: max. 66.67 MHz

Peripheral clock: max. 33.34 MHz

• Seven types of clock mode (selection of multiplication ratio of PLL1 and

PLL2, and selection external clock or crystal resonator)

Watchdog timer

(WDT)

• One-channel watchdog timer

Power-down

mode

• Supports power-down mode

Sleep mode

Software standby mode and hardware standby mode

Module standby mode

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