ACE25QC200GL datasheet(48/64 Pages) ACE

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ACE25QC200GL

2M BIT SPI NOR FLASH

VER 1.1

Enable Reset (66h) and Reset Device (99h)

Because of the small package and the limitation on the number of pins, the ACE25QC200GL provide a

software Reset instruction instead of a dedicated RESET pin. Once the Reset instruction is accepted, any

on-going internal operations will be terminated and the device will return to its default power-on state and

lose all the current volatile settings, such as Volatile Status Register bits, Write Enable Latch (WEL) status,

Program/Erase Suspend status, Continuous Read Mode bit setting (M7-M0) , Wrap Bit setting (W6-W4).

To avoid accidental reset, both instructions must be issued in sequence. Any other instructions other than

“Reset (99h)” after the “Enable Reset (66h)” instruction will disable the “Reset Enable” state. A new

sequence of “Enable Reset (66h)” and “Reset (99h)” is needed to reset the device. Once the Reset

instruction is accepted by the device, the device will take tRST to reset. During this period, no instruction

will be accepted.

Data corruption may happen if there is an on-going or suspended internal Erase or Program operation

when Reset instruction sequence is accepted by the device. It is recommended to check the WIP bit and

the SUS bit in Status Register before issuing the Reset instruction sequence.

Figure38. Enable Reset and Reset instruction Sequence

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