ACE25QC200GL datasheet(39/64 Pages) ACE

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ACE25QC200GL

2M BIT SPI NOR FLASH

VER 1.1

32KB Block Erase (52h)

The 32KB Block Erase instruction sets all memory within a specified block (32K-bytes) to the erased state

of all 1s (FFh). A Write Enable instruction must be executed before the device will accept the 32KB Block

Erase Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin

low and shifting the instruction code “52h” followed a 24-bit block address (A23-A0). And the address

A14-A0 is an unrelated item and has no effect on the result of the instruction. The Block Erase instruction

sequence is shown in Figure30.

The /CS pin must be driven high after the eighth bit of the last byte has been latched. If this is not done the

32KB Block Erase instruction will not be executed. After /CS is driven high, the self-timed 32KB Block

Erase instruction will commence for a time duration of tBE1 (See AC Characteristics). While the 32KB

Block Erase cycle is in progress, the Read Status Register instruction may still be accessed for checking

the status of the WIP bit. The WIP bit is a 1 during the 32KB Block Erase cycle and becomes a 0 when the

cycle is finished and the device is ready to accept other instructions again. After the 32KB Block Erase

cycle has finished the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The 32KB Block

Erase instruction will not be executed if the addressed page is protected by the Block Protect (BP4, BP3,

BP2, BP1, and BP0) bits.

Figure30. 32KB Block Erase Instruction

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