HMC8191LC4TR-R5 datasheet(43/44 Pages) AD

43 / 44 page

Data Sheet

HMC8191

Rev. C | Page 43 of 44

SOLDERING INFORMATION AND RECOMMENDED

LAND PATTERN

Figure 155 shows the recommended land pattern for the

HMC8191. The HMC8191 is contained in a 4 mm × 4 mm

24-terminal, ceramic, LCC package, with an exposed ground

pad (EPAD). This pad is internally connected to the ground of

the chip. To minimize thermal impedance and ensure electrical

performance, solder the pad to the low impedance ground

plane on the PCB. It is recommended that the ground planes on

all layers under the pad be stitched together with vias, to further

reduce thermal impedance.

The land pattern on the HMC8191 evaluation board provides a

simulated thermal resistance (θJA) of 38.3°C/W.

Figure 155. Evaluation Board Layout for the HMC8191 Package

EVALUATION BOARD INFORMATION

The EV1HMC8191LC4 evaluation board PCB used in the

application must use RF circuit design techniques. Signal lines

must have a 50 Ω impedance and connect the package ground

leads and exposed pad directly to the ground plane similar to

the setup shown in Figure 156. Use a sufficient number of via

holes to connect the top and bottom ground planes.

LO, J2

RF, J1

HMC8191

IF1, J3

IF2, J4

Figure 156. EV1HMC8191LC4 Evaluation Board PCB, Top Layer

Table 6. Bill of Materials for the EV1HMC8191LC41 Evaluation Board PCB

Quantity

Reference Designator

Description

Manufacturer

Part Number

PCB, EV1HMC8191LC42

Analog Devices

08_040858a

J1 to J4

2.92 mm SMA connectors, SRI Connector Gage

SRI Connector Gage Co.

25-146-1000-92

Device under test, HMC8191

Analog Devices

HMC8191

Reference this number when ordering the evaluation board PCB.

Circuit board material: Rogers 4350.

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