EMC1702 datasheet(17/60 Pages) MICROCHIP

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EMC1702



2020 Microchip Technology Inc.

DS20006455A

All SMBus Data bytes are sent most significant bit first and composed of 8-bits of information.

3.1.3

SMBus ACK and NACK Bits

The SMBus client will acknowledge all data bytes that it receives (as well as the client address if it

matches and the ARA address if the ALERT pin is asserted). This is done by the client device pulling

the SMBus Data line low after the 8th bit of each byte that is transmitted.

The host will NACK (not acknowledge) the data received from the client by holding the SMBus data

line high after the 8th data bit has been sent.

3.1.4

SMBus Stop Bit

The SMBus Stop bit is defined as a transition of the SMBus Data line from a logic ‘0’ state to a logic

‘1’ state while the SMBus clock line is in a logic ‘1’ state. When the EMC1702 detects an SMBus Stop

bit, and it has been communicating with the SMBus protocol, it will reset its client interface and prepare

to receive further communications.

3.1.5

SMBus Time-out

The EMC1702 includes an SMBus time-out feature. Following a 30ms period of inactivity on the

SMBus, the device will time-out and reset the SMBus interface.

The time-out functionality defaults to disabled and can be enabled by writing to the TIMEOUT bit (see

Section 5.12).

3.1.6

SMBus and I2C Compliance

The major differences between SMBus and I2C devices are highlighted here. For complete compliance

information, refer to the SMBus 2.0 specification.

1. Minimum frequency for SMBus communications is 10kHz.

2. The client protocol will reset if the clock is held at a logic ‘0’ for longer than 30ms. This time-out

functionality is disabled by default.

3. The client protocol will reset if both the clock and data lines are held at a logic ‘1’ for longer than

150us. This function is disabled by default.

4. I2C devices do not support the Alert Response Address functionality (which is optional for SMBus).

560

1001_001(r/w)

9100

0101_100(r/w)

750

1001_010(r/w)

20000

0101_101(r/w)

1270

1001_011(r/w)

Open

0011_000(r/w)

Table 3.1 ADDR_SEL Resistor Setting (continued)

RESISTOR (5%)

SMBUS ADDRESS

RESISTOR (5%)

SMBUS ADDRESS

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