EMC1702 datasheet(16/60 Pages) MICROCHIP

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EMC1702

DS20006455A



2020 Microchip Technology Inc.

Chapter 3 Communications

3.1

System Management Bus Interface Protocol

The EMC1702 communicates with a host controller, such as an SIO, through the SMBus. The SMBus

is a two-wire serial communication protocol between a computer host and its peripheral devices. A

detailed timing diagram is shown in Figure 3.1. Stretching of the SMCLK signal is supported; however,

the EMC1702 will not stretch the clock signal.

3.1.1

SMBus Start Bit

The SMBus Start bit is defined as a transition of the SMBus Data line from a logic ‘1’ state to a logic

‘0’ state while the SMBus Clock line is in a logic ‘1’ state.

3.1.2

SMBus Address and RD / WR Bit

The SMBus Address Byte consists of the 7-bit client address followed by a 1-bit RD / WR indicator. If

this RD / WR bit is a logic ‘0’, the SMBus host is writing data to the client device. If this RD / WR bit

is a logic ‘1’, the SMBus host is reading data from the client device.

The EMC1702 SMBus address is determined by a single resistor connected between ground and the

ADDR_SEL pin as shown in Table 3.1.

Figure 3.1 SMBus Timing Diagram

Table 3.1 ADDR_SEL Resistor Setting

RESISTOR (5%)

SMBUS ADDRESS

RESISTOR (5%)

SMBUS ADDRESS

1001_100(r/w)

1600

0101_000(r/w)

100

1001_101(r/w)

2000

0101_001(r/w)

180

1001_110(r/w)

2700

0101_010(r/w)

300

1001_111(r/w)

3600

0101_011(r/w)

430

1001_000(r/w)

5600

0101_100(r/w)

SMDATA

SMCLK

BUF

S - Start Condition

P - Stop Condition

T HIGH

T LOW

T HD:STA

T SU:STO

T HD:STA T HD:DAT

T SU:DAT

T SU:STA

T FALL

T RISE

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