INA237 datasheet(20/48 Pages) TI

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The INA237-Q1 supports the transmission protocol for fast mode (1 kHz to 400 kHz) and high-speed mode (1

kHz to 2.94 MHz). All data bytes are transmitted most significant byte first and follow the SMBus 3.0 transfer

protocol.

To communicate with the INA237-Q1, the main device must first address secondary devices through a

secondary device address byte. The secondary device address byte consists of seven address bits and a

direction bit that indicates whether the action is to be a read or write operation.

The device has two address pins, A0 and A1. Table 7-2 lists the pin logic levels for each of the 16 possible

addresses. The device samples the state of pins A0 and A1 on every bus communication. Establish the pin

states before any activity on the interface occurs. When connecting the SDA pin to either A0 or A1 to set the

device address, additional hold time of 100 ns is needed on the MSB of the I2C address to insure correct device

addressing.

Table 7-2. Address Pins and Secondary Device Addresses

Secondary Device Address

GND

1000000

GND

1000001

GND

SDA

1000010

GND

SCL

1000011

GND

1000100

1000101

SDA

1000110

SCL

1000111

SDA

GND

1001000

SDA

1001001

SDA

1001010

SDA

SCL

1001011

SCL

GND

1001100

SCL

1001101

SCL

SDA

1001110

SCL

1001111

7.5.1.1 Writing to and Reading Through the I2C Serial Interface

Accessing a specific register on the INA237-Q1 is accomplished by writing the appropriate value to the register

pointer. Refer to Section 7.6 for a complete list of registers and corresponding addresses. The value for the

the R/W bit low. Every write operation to the device requires a value for the register pointer.

Writing to a register begins with the first byte transmitted by the main device. This byte is the secondary

device address, with the R/W bit low. The device then acknowledges receipt of a valid address. The next

byte transmitted by the main device is the address of the register to be accessed. This register address value

updates the register pointer to the desired internal device register. The next two bytes are written to the register

addressed by the register pointer. The device acknowledges receipt of each data byte. The main device may

terminate data transfer by generating a start or stop condition.

When reading from the device, the last value stored in the register pointer by a write operation determines which

be written to the register pointer. This write is accomplished by issuing a secondary device address byte with

the R/ W bit low, followed by the register pointer byte. No additional data are required. The main device then

generates a start condition and sends the address byte for the secondary device with the R/W bit high to initiate

the read command. The next byte is transmitted by the secondary device and is the most significant byte of the

the secondary device transmits the least significant byte. The main device may or may not acknowledge receipt

INA237-Q1

SBOSA27A – JUNE 2020 – REVISED JUNE 2021

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