INA237 datasheet(19/48 Pages) TI

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Shunt Voltage

Temperature

Bus Voltage

ALERT

(ALATCH = 0)

(APOL = 0)

(CNVR = 1)

Power

Shunt Over Voltage Threshold

Bus Under Voltage Threshold

Over Temp Threshold

Power Over Limit Threshold

BUV

SET

SOV

SET

BUV

CLEAR

SOV

BUV

SET

SOV

CLEAR

BUV

SET

BUV

SET

- No diag. error -

Conversion Complete

Reported

Figure 7-6. Multi-Alert Configuration

7.4 Device Functional Modes

7.4.1 Shutdown Mode

In addition to the two conversion modes (continuous and triggered), the device also has a shutdown mode

(selected by the MODE bits in ADC_CONFIG register) that reduces the quiescent current to less than 5 µA and

turns off current into the device inputs, reducing the impact of supply drain when the device is not being used.

The registers of the device can be written to and read from while the device is in shutdown mode. The device

remains in shutdown mode until another triggered conversion command or continuous conversion command is

received.

The device can be triggered to perform conversions while in shutdown mode. When a conversion is triggered,

the ADC will start conversion; once conversion completes the device will return to the shutdown state.

Note that the shutdown current is specified with an inactive communications bus. Active clock and data activity

will increase the current consumption as a function of the bus frequency as shown in Shutdown IQ vs. Clock

Frequency.

7.4.2 Power-On Reset

Power-on reset (POR) is asserted when VS drops below 1.26V (typical) at which all of the registers are reset to

their default values. A manual device reset can be initiated by setting the RST bit in the CONFIG register. The

default power-up register values are shown in the reset column for each register description. Links to the register

descriptions are shown in Section 7.6.

7.5 Programming

7.5.1 I2C Serial Interface

The INA237-Q1 operates only as a secondary device on both the SMBus and I2C interfaces. Connections

to the bus are made through the open-drain SDA and SCL lines. The SDA and SCL pins feature integrated

spike suppression filters and Schmitt triggers to minimize the effects of input spikes and bus noise. Although

the device integrates spike suppression into the digital I/O lines, proper layout techniques help minimize the

amount of coupling into the communication lines. This noise introduction could occur from capacitive coupling

signal edges between the two communication lines themselves or from other switching noise sources present

in the system. Routing traces in parallel with ground in between layers on a printed-circuit board (PCB) typically

reduces the effects of coupling between the communication lines. Shielded communication lines reduce the

possibility of unintended noise coupling into the digital I/O lines that could be incorrectly interpreted as start or

stop commands.

www.ti.com

INA237-Q1

SBOSA27A – JUNE 2020 – REVISED JUNE 2021

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