MCP3565R datasheet(77/108 Pages) MICROCHIP

77 / 108 page

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DS20006401C-page 77

MCP3565R

6.8.3

CRCCFG ERROR INTERRUPT

The CRCCFG interrupt happens when an error in the

CRC-16 checksum has been detected in the register

map CRC calculation.

This interrupt is implemented with two different and

independent mechanisms: STATUS byte on SDO and

IRQ register Status bit.

6.8.3.1

STATUS Byte on SDO

In case of a CRCCFG error on the next STATUS byte

transmitted on SDO, the CRCCFG_STATUS bit is logic

low. Once the STATUS byte has been transmitted, the

CRCCFG_STATUS bit appears as ‘1’ until a new

interrupt occurs. If the error is detected again between

two STATUS byte transmissions, the CRCCFG_STATUS

bit on SDO will appear as equal to ‘0’ on the second

reading.

6.8.3.2

IRQ Register Status Bit

In case of a CRCCFG error, the CRCCFG_STATUS bit

in the IRQ register is set to ‘0’. Once the IRQ register is

fully read, the CRCCFG_STATUS bit is reset to ‘1’. If

the CRCCFG error happens again between two read-

ings of the IRQ register, the IRQ register Status bit will

appear as ‘0’ on the second reading.

6.9

Master Clock Input/Output Modes

The MCP3565R device does not include a dedicated

input/output master clock pin. In the MCP3565R, the

SCK pin is used to enter the external Master Clock

(MCLK) for the ADC or to deliver the Analog Master

Clock to the MCU. The SCK pin can be bidirectional

and the direction of the SCK I/O is determined by the

CLK_SEL[1:0] bits setting. Additionally, the transitions

from Input to Output mode and vice-versa, need extra

care in order to avoid bus contention errors and induce

a specific sequence that allows smooth transitions.

These transitions are described in the following

sections and in Figure 6-13 to Figure 6-16. The follow-

ing sections detail precisely each possible mode of

operation as defined in Table 5-12.

6.9.1

INTERNAL OSCILLATOR MODE

WITHOUT EXTERNAL CLOCK

OUTPUT (CLK_SEL[1:0] = 10)

This mode is accessed by writing CLK_SEL[1:0] = 10.

This mode is the easiest to use, as SCK does not share

its functionality. In this mode, SCK is only the Serial

Clock Input for the SPI digital Interface. The Master

Clock (MCLK) is generated by the internal oscillator

and runs asynchronously with the Serial Clock (SCK).

The master clock is not propagated on any output.

Toggling the CS pin does not reset or impact the

internal MCLK clock generation.

6.9.2

EXTERNAL CLOCK MODE

(CLK_SEL[1:0] = 0x)

This mode is accessed by writing CLK_SEL[1:0] = 0x.

This mode defines the SCK pin as both the Serial Clock

Input and the Master Clock Input. In this mode, the

SCK and MCLK are equal, therefore the device

becomes a fully synchronous system. If the ADC is not

in Conversion mode, the SCK input clock has no

restrictions, but if the ADC is running, the SCK input

clock should be continuous and its frequency should be

kept constant to ensure the optimal performance of the

ADC. During this Free-Running Clock mode, the SPI

communications should not impact the clock frequency

and need to be synchronized on the SCK input.

Toggling the CS pin does not reset or impact the MCLK

clock input. SCK always remains an MCLK input in this

mode, even when CS is logic high, while the SPI

commands are not taken into account anymore. Using

a MCU that can be set in Framed SPI mode can help to

design a fully synchronous system. The MCU can

continuously send frames at the same frequency,

where some frames are simply clock frames with no

communication (CS is kept logic high) and some

frames include communications (CS kept logic low and

SDI can toggle to define commands). Therefore, the

toggling of the CS input is synchronized with the

free-running clock, SCK, so that the communications

can happen at any desired time without impacting the

SCK continuous clocking.

Since the SCK pin remains as an input for both

CLK_SEL[1:0] = 0x and 10 modes, the transition from

one to another is instantaneous, as soon as the write

command is completed (end of last bit of the CONFIG0

resets any current conversion and resets the internal

clock phases in order to restart from a unique pre-

defined Reset state. Respecting the SPI timings

ensures that the transition from one mode to another is

handled properly by the device. When a transition to

CLK_SEL[1:0] happens, the internal oscillator is

restarted from a Shutdown state and the start-up time

of the oscillator is necessary to ensure that the internal

clock frequency is settled to a stable final value.

Figure 6-13 and Figure 6-14 show in detail the transi-

tions from and to CLK_SEL[1:0] = 0x and 10 modes for

the MCP3565R device. In Figure 6-14, the prescaler is

set to PRE[1:0] = 00 (1:1) so that AMCLK = MCLK.

Note:

If MCLK starts running before the device

is locked, an interrupt can momentarily

occur, even if registers have not been cor-

rupted. In such a case, the user must send

a start/restart conversion Fast command,

which clears the unwanted interrupt and

correctly restarts the CRC calculations.

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