Connection Diagrams

20138902

Top View

20138903

Bottom View

10–Bump Thin Micro SMD Package, Large Bump

See NS Package Number TLP10NHA

Order Information

Order Number

Package Marking (Note)

Supplied As

LM3204TL

XYTT SJDB

250 Units, Tape and Reel

LM3204TLX

XYTT SJDB

3000 Units, Tape and Reel

Note: The package marking “XY” designates the date code. “TT” is a NSC internal code for die traceability.

Pin Description

Pin #

Name

Description

A1

V

DD

Analog Supply Input. A 0.1µF ceramic capacitor is recommended to be placed as close to this pin

as possible. (Figure 1)

B1

V

CON

Voltage Control Analog input. V

leave floating.

C1

FB

Feedback Analog Input. Connect to the output at the output filter capacitor. (Figure 1)

D1

BYP

normal operation.

D2

EN

D3

PGND

Power Ground

C3

SW

Switching Node connection to the internal PFET switch and NFET synchronous rectifier.

Connect to an inductor with a saturation current rating that exceeds the maximum Switch Peak

Current Limit specification of the LM3204.

B3

PV

IN

Power Supply Voltage Input to the internal PFET switch and Bypass FET. (Figure 1)

A3

BYPOUT

Bypass FET Drain. Connect to the output capacitor. (Figure 1) Do not leave floating.

A2

SGND

Analog and Control Ground

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