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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AD8316 датащи(PDF) 2 Page - Analog Devices |
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AD8316 датащи(HTML) 2 Page - Analog Devices |
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2 / 20 page  REV. C –2– AD8316–SPECIFICATIONS (V POS = 2.7 V, TA = 25 C, 52.3 on RFIN, unless otherwise noted.) Parameter Conditions Min Typ Max Unit OVERALL FUNCTION Frequency Range 1 To Meet All Specifications 0.1 2.5 GHz Input Voltage Range ±1 dB Log Conformance, 0.1 GHz –58.6 –10 dBV Equivalent dBm Range –45.6 +3 dBm Logarithmic Slope 2, 3 0.1 GHz 20.5 22.1 24.5 mV/dB Logarithmic Intercept 2, 3 0.1 GHz –68 –74 –78 dBV Equivalent dBm Level –55 –61 –65 dBm RF INPUT INTERFACE Pin RFIN Input Resistance 4 0.1 GHz 2.9 k Ω Input Capacitance 4 0.1 GHz 1.0 pF OUTPUTS Pins OUT1 and OUT2 Minimum Output Voltage VSET ≤ 200 mV, ENBL High, RF Input ≤ –60 dBm 0.1 0.15 0.25 V ENBL Low 0.025 V Maximum Output Voltage RL > 800 Ω 2.45 2.6 V General Limit 2.7 V ≤ V POS ≤ 5.5 V VPOS – 0.1 V Output Current Drive Source 12 mA Output Buffer Noise 25 nV/ √Hz Output Noise RF Input = 2 GHz, 0 dBm, 100 nV/ √Hz CFLT = 220 pF, fNOISE = 400 kHz Small Signal Bandwidth 0.2 V to 2.6 V Swing 30 MHz Slew Rate 10%–90%, 250 mV Step (VSET), Open Loop 5 20 V/ µs Full-Scale Response Time FLTR = Open; Refer to TPC 28 50 ns SETPOINT INTERFACE Pin VSET Nominal Input Range Corresponding to Central 50 dB 0.25 1.5 V Logarithmic Scale Factor 43.5 dB/V Input Resistance 100 k Ω Slew Rate 16 V/ µs ENABLE INTERFACE Pin ENBL Logic Level to Enable Power 1.8 VPOS V Input Current when Enable High 20 µA Logic Level to Disable Power 0.8 V Enable Time Time from ENBL High to VAPC within 1% of 7 µs Final Value, CFLT = 68 pF; Refer to TPC 20 Disable Time Time from ENBL Low to VAPC within 1% of 3 µs Final Value, CFLT = 68 pF; Refer to TPC 20 Power-On/Enable Time Time from VPOS/ENBL Low to VAPC within 3 µs 1% of Final Value, CFLT = 68 pF; Refer to TPC 25 Power-Off/Disable Time Time from VPOS/ENBL High to VAPC within 4 µs 1% of Final Value, CFLT = 68 pF; Refer to TPC 25 BAND SELECT INTERFACE Pin BSEL Logic Level to Enable OUT1 1.8 VPOS V Input Current when BSEL High 50 µA Logic Level to Enable OUT2 0.0 1.7 V POWER INTERFACE Pin VPOS Supply Voltage 2.7 5.5 V Quiescent Current ENBL High 8.5 10.7 mA Over Temperature –30 °C ≤ T A ≤ +85°C12 mA Disable Current 6 ENBL Low 3 10 µA Over Temperature –30 °C ≤ T A ≤ +85°C13 µA NOTES 1Operation down to 0.02 GHz is possible. 2Calculated over the input range of –40 dBm to –10 dBm. 3Mean and standard deviation specifications are in Table I. 4See TPC 9 for plot of Input Impedance vs. Frequency. 5Response time in a closed-loop system will depend upon the filter capacitor (C FLT) used and the response of the variable gain element. 6This parameter is guaranteed but not tested in production. The maximum specified limit on this parameter is the +6 sigma value from characterization. Specifications subject to change without notice. |
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