REV. C

AD8316

–13–

AD8316

OUT2

FLT2

VPOS

OUT1

COMM

FLT1

BSEL

RFIN

ENBL

VSET

1

2

3

4

5

10

9

8

7

6

RFIN

R1

52.3

C1

0.1 F

2.7 TO 5.5V

Figure 6. Basic Connections (Shown with MSOP Pinout)

OUT1

DIRECTIONAL

COUPLER

OUT2

FLT2

VSET

FLT1

RFIN

R1

52.3

ATTN

DAC

GAIN

CONTROL

VOLTAGES

RFIN1

BSEL

BAND

SELECT

RFIN2

RX1

RX2

TX1

TX2

ANT

PWR

AMP

Figure 7. Block Diagram of Typical Application

A supply voltage of 2.7 V to 5.5 V is required for the AD8316.

The supply to the VPOS pin should be decoupled with a low

inductance 0.1

µF surface-mount ceramic capacitor close to the

device. The AD8316 has an internal input coupling capacitor,

which negates the need for external ac coupling. This capacitor,

along with the device’s low frequency input impedance of approxi-

mately 3.0 k

Ω, sets the minimum usable input frequency to around

20 MHz. A broadband 50

Ω input match is achieved in this

example by connecting a 52.3

Ω resistor between RFIN and

ground (COMM). A plot of input impedance versus frequency

is shown TPC 9. Other matching methods are also possible

(see the Input Coupling Options section).

In a power control loop, the AD8316 provides both the detector

and controller functions.

A number of options exist for coupling the RF signal from the

power amplifiers (PA) to the AD8316 input. Because only one

PA output is active at any time, a single RF input on the

AD8316 is sufficient in all cases.

Two directional couplers can be used directly at the PA outputs.

The outputs of these couplers would be passively combined

before being applied to the AD8316 RF input (in general,

some additional attenuation will be required between the coupler

and the AD8316). Another option involves using a dual-direc-

tional coupler between the PA and T/R switch. This device has

two inputs/outputs and a single-coupled output so that no exter-

nal combiner is required.

A third option is to use a single broadband directional coupler

at the output of the transmit/receive (T/R) switch (the outputs

from the two PAs are combined in the T/R switch). This is

shown in Figure 7. This provides the advantage of enabling the

power at the output of the T/R switch to be precisely set, elimi-

nating any errors due to insertion loss and insertion loss

variations of the T/R switch.

A setpoint voltage is applied to VSET from the controlling

source, generally a DAC. Any imbalance between the RF input

level and the level corresponding to the setpoint voltage will be

corrected by the selected output, OUT1 or OUT2, which drives

the gain control terminal of the PAs. This restores a balance

between the actual power level sensed at the input of the AD8316

and the demanded value determined by the setpoint. This assumes

that the gain control sense of the variable gain element is posi-

tive; that is, an increasing voltage from OUT1 or OUT2 will

tend to increase gain. The outputs can swing from 100 mV

above ground to within 100 mV of the supply rail and can source

up to 12 mA. (A plot of maximum output voltage versus output

current is shown in TPC 19.) OUT1/OUT2 are capable of

sinking more than 200

µA.

Range on VSET and RF Input

The relationship between RF input level and the setpoint volt-

age follows from the nominal transfer function of the device (see

TPCs 2, 3, 5, and 6). At 0.9 GHz, for example, a voltage of 1 V

on VSET indicates a demand for –17 dBm (–30 dBV) at RFIN.

The corresponding power level at the output of the power ampli-

fier will be greater than this amount due to the attenuation

through the directional coupler. For setpoint voltages of less

than approximately 200 mV and RF input amplitudes greater

at its minimum level of approximately 250 mV. This feature can

be used to prevent any spurious emissions during power-up and

power-down phases. Above 250 mV, VSET will have a linear

control range up to 1.4 V, corresponding to a dynamic range of

49 dB. This results in a slope of 22.2 mV/dB or approximately

45.5 dB/V.

Transient Response

The time domain response of power amplifier control loops,

using any kind of controller, is only partially determined by the

choice of filter which, in the case of the AD8316, has a true

integrator form 1/sT, as shown in Equation 7, with a time con-

stant given by Equation 8. The large signal step response is also

strongly dependent on the form of the gain control law. Never-

theless, some simple rules can be applied. When the filter capacitor

but the incremental bandwidth of this loop will still vary as

shown in Figure 5. This bandwidth will be highest at the

point where the slope of the tangent drawn on this curve is

greatest—that is, for power outputs near the center of the PA’s

range—and will be much reduced at both the minimum and the

maximum power levels, where the slope of the gain control

curve is lowest, due to its S-shaped form. Using smaller values

proportion to its value. Eventually, however, a secondary effect

will appear, due to the inherent phase lag in the power amplifier’s

control path, some of which may be due to parasitic or deliber-

ately added capacitance at the OUT1 and OUT2 pins. This results

in the characteristic poles in the ac loop equation moving off the

real axis and thus becoming complex (and somewhat resonant).

This is a classic aspect of control loop design.

experimentally for a particular amplifier and circuit board lay-

range from 150 pF to 300 pF.

In many cases, some improvement in the worst-case response

time can be achieved by including a small resistance in series with

fer function, which will serve to cancel some of the higher-order